Test Sockets

 RF Test Sockets Johnstech

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DDR4 - Micron APP Notes

TN-40-40: DDR4 Point-to-Point Design Guide - Micron

https://media-www.micron.com › products › dram

TN-40-41: Adding ECC With DDR4 x16 Components - Micron ...

https://www.micron.com › technical-note › dram

Aligni - Unified PLM

 Aligni URL: Unified PLM and MRP for high-tech manufacturers

BGA - Rework and Reball

BGA and PCB Rework Services

Microelectronics packaging, device design and manufacturing - ISI

BGA Rework Stations & PCB Rework Services - Precision PCB Services

Circuit board rework and repair - BGA component rework and repair

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Lord Kelvin's Quote

 

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Electronic Tutorials

If you are looking for some good Electronic educational material try . . . 

Electronics Tutorials

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Ethernet Design Guidelines

"The total length of each MII trace should be less than 6 inches, or 6000 mils. The traces should be length matched within 20 mils for 1G transmissions and length-matched within 50 mils for 100M or 10M transmissions. RX traces must be length-matched to the other RX traces, and TX traces must be length-matched to the other TX traces. The number of vias and stubs on the MII traces should be kept to a minimum."  

Magnetic Isolation No metal should be under the magnetics on any layer. If metal is needed under the magnetics, it must be separated by a ground plane at the least. Metal under the RJ45 connector with integrated magnetic is allowed.

Source Texas Instruments: 

Ethernet PHY PCB Design Layout Checklist - Texas Instruments

Chassis / GND for RJ45 with Integrated Magnetics 

Source NXP APP Note 4215:

https://www.nxp.com/docs/en/application-note/AN4215.pdf

Layout Considerations for Pulse Ethernet Magnetics

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