Saturday, June 23, 2012
Wednesday, June 20, 2012
Friday, June 15, 2012
Sunday, June 10, 2012
Saturday, June 9, 2012
Controlled Impedance
Controlled Impedance Articles:
Which Impedance Calculator is Right ? Randy Clemmons
What is Characteristic Impedance - Eric Bogatin
Optimizing Impedance Discontinuities of SMD Pads Altera - AN-530
Online Trace Impedance Calculator Links:
cgi-wcalc - Dan McMahill
Desktop Trace Impedance Calculator Links:
AWR TxLine 2003 (Free) Excellent Tool
Rogers MWI-2014 Software (Free)
Saturn PCB Toolkit (Free) - PCB Design Calculator
UltraCAD Design Inc. (Free / Buy) - Douglas Brooks
ICD has a Stackup Calculator and Offers a 14 Day Evaluation
ICD has a Stackup Calculator and Offers a 14 Day Evaluation
VIA Impedance:
Designing Controlled-impedance Vias Thomas Neu - Texas Instruments
The Poor Man’s PCB Via Modeling Methodology Bert Simonovich's Design Notes
Wednesday, June 6, 2012
Monday, June 4, 2012
Metric Stuff - Tom Hausherr
Tom has been a big contributor in the PCB Design Community. Tom has created many useful tables and written numerous excellent papers:
Inch to Metric Conversion Tables for PCB Design
Sunday, June 3, 2012
Signal Integrity
Signal layers should always be adjacent to ground or power planes.
Signal layers should be tightly coupled to their adjacent planes.
Route traces orthogonally (at right angles) on adjacent layers.
Power and ground planes should be closely coupled together. Drilled Holes will effect the actual plane capacitance value.
Multiple-ground planes are very advantageous.
High speed signals should be routed on buried layers and located between planes.
When critical signals are routed on more than one layer they should be
confined to the two layers adjacent to the same plane.
If the two routing layers are not adjacent to the same plane, you should
drop return path vias at each signal via in the routed path.
To Minimize Crosstalk in Single-Ended Traces (Not Diff Pairs):
Digital circuits with internal traces (Stripline Traces) should be
separated by at least the distance to the nearest ground or power plane.
For example if H=0.006" (0.15mm) then the traces should be separated by
at least 0.006" (0.15mm).
Digital circuits with external traces (Microstrip Traces) should be
separated by at least twice the distance to the nearest ground or power
plane.
For example if H=0.006" (0.15mm) then the traces should be separated by
at least 0.012"(0.3mm).
The general rule of thumb to minimize crosstalk to 10% or less is as
follows: 50 Ohm traces should be spaced as suggested in the stripline
and microstrip examples shown above.
Basically, on FR4 keep 50 ohm lines separated at least one line width.
Use the 20H Power Plane Rule to Minimize Radiated EMI from the PCB edges:
The power plane should be pulled back from the edge of GND planes by a factor of 20 x the dielectric
thickness between the power and ground planes. For example with a dielectric thickness of 4mils the
power plane would be pulled in on all sides of the GND plane by 80mils (4x20).
Signal Integrity Links:
Common Mode Ground Currents:
Common Mode Ground Currents Dr. Howard Johnson
Crosstalk:
Crosstalk Modes Power Point Slides - Intel
Crosstalk Explained PDF - Douglas Brooks
Crosstalk Calculator Web Calculator - EEWeb
Power Distribution Networks Design:
Advanced Power Delivery IPBLOX
Discrete Components:
SRF & PRF for RF Capacitors Johanson
Phase Shifts:
Source of Phase Shift ECE 209 - Wikipedia
Phase Difference Simulator Jave Applet - Wikipedia
Thumb Rules:
- To Maintain Cross Sectional area of a Controlled Impedance Route the VIA Diameter should Equal 1/3 Trace Width.
- Via stitching of 1/10th wave length can suppress radiated signals approximatley 25dB.
Friday, June 1, 2012
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