Solder Mask

PCB Solder Mask | Printed Circuit Board Manufacturing | MADPCB

6 Common Solder Mask Errors in PCBs | Sierra Circuits

Exploring Paste Mask & Solder Mask in Your PCB Footprint - Altium YouTube

An Overview of LPI Soldermask and the PCB Manufacturing Process

An Overview of LPI Soldermask and the PCB Manufacturing Process | Bay Area Circuits:














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Guidelines for SMT Assembly of 0201 DSN Package

Sources:

http://www.onsemi.com/pub_link/Collateral/AND9107-D.PDF

http://www.onsemi.com/pub_link/Collateral/AND8398-D.PDF


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TPS8267x 600-mA, High-Efficiency MicroSiP Step-Down Converter

The TPS8267x datasheet also has some good layout advice for uGBAs.

click on image to view

Source: http://www.ti.com/product/tps82671

Soldermask and QFPs

Here is an interesting statement about soldermask.

"By the way, don't assume that putting fingers of resist between pads on an otherwise bare board might help overcome bridging, because most bridging occurs between component leads above the board. You are just adding to the cost by using a more expensive process, and gaining little."

Source: PCB Solder Mask Design Basics - Standards, Materials and Processes:


Some points to consider:

Solder mask thickness is typically ~ 0.5mil thick.

Copper pads on outer layer are typically 1.4 to 2.0 mil thick. 

Solder paste thickness is typically ~ 5mil thick.

The copper pads are 3 to 4 times thicker (taller) than the soldermask.

The 5mil thick solder paste on top of copper pad is 10 times thicker (taller) than the soldermask.  

And the paste is sitting top of the copper pads.

click on image to view

Does soldermask between the pads really help prevent solder bridging ?

For fine pitch QFPs you may want to use ganged soldermask.

Something to think about.

Close up of solder paste on two adjacent pins.

That's It !

Soldermask thickness

Soldermask thickness:

Dated, but interesting dialog on SMT forum.

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Soldermask - TAIYO PSR-4000BN Series

Data Sheet for PSR-4000 BN - TAIYO America


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Soldermask 1:1

PCB Fabricators prefer the supplied soldermask and pad data to be 1:1.

When your PCB data goes to fabrication the soldermask layers are examined to determine if apertures have been modified (are not 1:1).

If your soldermask layers are not 1:1 then the fabricator will most likely NOT use your soldermask layers and they will try to use the solder paste layer to determine the actual pad sizes.

Fabricators shrink or expand the soldermask to optimize your design for best process yields. 

Soldermask webs are removed if the soldermask features between pads of fine-pitch parts are less that 3 mils wide.  

Gang mask is a term used to describe removing the soldermask between closed spaced pins.

Here is and example of a gang masked (SOIC, SOP) with a pin to pin pitch of 0.65mm.

Laser Direct Imaging (LDI) has greatly  improved soldermask registration and reduced the soldermask swell requirements, which allow for wider soldermask webs around fine pitch parts.

I'm on a mission this month to determine what is currently the best practice for soldermask. 

Should we provide 1:1 data to the fabricators ?

Research:

According to Tom H. who is the father and Champion of the IPC-7351 Land patterns:

Designers have two choices.

"Use a stock library with 1:1 scale masks and create fabrication and assembly notes for solder mask and paste mask adjustments".

"Create a custom library for a PCB layout and tell the manufacturer's not to touch (adjust) the Gerber data."

Source:
http://www.pcblibraries.com/forum/advice-for-solder-mask-paste-mask-layers_topic484.html

PCB Libraries has created a CAD tool neutral CAD Library Solution for Land Patterns.
http://www.pcblibraries.com/

By default this tool creates pads and soldermask 1:1.

Winonics | Printed Circuit Boards | Prototypes - Production - Quick Turn Arounds | Brea, CA

Winonics | Printed Circuit Boards | Prototypes - Production - Quick Turn Arounds | Brea, CA:

See Products and Services for DFM (Design for Manufacture) recommendations.


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Soldermask on via-holes with ENIG finish.

Source: Soldermask on via-holes - Eurocircuits Printed circuits blog | Eurocircuits: 

"For closed via-holes we have developed an alternative solution which avoids chemicals getting trapped in the partially closed via-holes during developing of the soldermask or during application of the Ni/Au. 

Before the coating the entire panel with soldermask we selectively print soldermask into the via holes using a stencil. During a second print run we then cover the whole panel. 

This way the via-holes are completely filled with soldermask. An even layer of soldermask now covers the via-holes leaving no pockets to hold residual chemicals. 

We have used this technique for over 6 months, and it has proved successful in dramatically reducing the number of skip pad problems."

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Via Plugging Methods - Pros and Cons

Plug Via Process Requirements - Circuit Board Manufacturing Solutions | Epec Engineered Technologies:

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VIA Barrel Reliefs - Soldermask

Using Soldermask Barrel Reliefs can provide a reliable low cost alternative to using fills and plugs.

Vias with Finished Holes Sizes greater than 18mils that are NOT FILLED should be un-tented using Soldermask Barrel Reliefs. 

When the nominal finished hole sizes of vias are larger than 18mils fabricators may request to add barrel reliefs to the soldermask.  

Some Fabricators will tent vias with holes sizes as large as 23mils (0.6mm) using LPI soldermask. Larger holes may require additional processing steps.

Consult with your fabricator when using soldermask barrel reliefs. The hole size threshold and soldermask relief requirements for using barrel reliefs will vary from fabricator to fabricator. 

The soldermask reliefs are typically specified as finished hole size + 6mils.

For vias with hole sizes smaller than 18mils (0.45mm) fabricators can fully tent the vias on both sides of the board using LPI soldermask application techniques.

For vias with hole sizes larger than 18mils soldermask barrel reliefs can be used to minimize problems associated with trapped etching and plating solutions.  

The open vias allow for rinsing and cleaning of the via barrels after the finished plating process, this reduces trapped corrosive chemicals in the via barrels.


Top Layer View

Bottom Layer View

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Other things to Consider

When using barrel reliefs for vias the minimum soldermask web rules need to be considered. 

A barrel relief via needs to be placed farther away from the component pad than a completely tented via.

As shown above the via at R220 will violate the 4mil (0.1mm) minimum soldermask web rule. 

See C221 for a good example which has greater than 4mils of soldermask web.

Test Points

Un-tented vias can be used as test points.  The exposed vias can also be useful for prototypes where cuts and jumpers may need to be applied.

ICT Testing with Vacuum Systems 

If you plan to use an In Circuit Tester (ICT) with a vacuum system you may not want to use barrel reliefs.  

A large number of holes in the board may limit the vacuum system's ability to properly mate the the board with the test probes. 

Silkscreen on exposed vias. 

When using barrel reliefs on vias, as shown below it can be difficult to avoid having some silkscreen printed on barrel relieved vias.  

You may need to adjust your design rules and fab notes to accommodate the silkscreen, or position the silkscreen to avoid printing ink in the via holes.

Avoid using unfilled one-side tented VIAs ! ! !

Tenting vias only on one side can cause problems. Trapped etching chemicals in vias will corrode the barrel walls and create open circuits over time.

Workarounds

You may be able to avoid using barrel reliefs by simply using smaller vias that do not require additional process steps.

To handle higher current requirements consider using 2-3 small vias instead of using one large via.

Soldermask - VIA Encroaching

VIA Encroaching can be used to enhance thermal conductivity of the QFN packages.

http://www.cirrus.com/jp/pubs/appNote/AN315REV1.pdf

Soldermask Design Basics - Standards, Materials and Processes | Epec Engineered Technologies

"By the way, don't assume that putting fingers of resist between pads on an otherwise bare board might help overcome bridging, because most bridging occurs between component leads above the board. You are just adding to the cost by using a more expensive process, and gaining little."

Source: Soldermask Design Basics - Standards, Materials and Processes | Epec Engineered Technologies:

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VIA Plugging Guide

This excellent article covers VIA plugging using inks and soldermask.

IPC-4671, PCB Via Structures, Bumped, Dimpled, Planarized