PCB Designer: September 2015

Tuesday, September 22, 2015

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Validation of DDR2/3 Designs

Validation of DDR2/3 Designs Agilent

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DDR Memory Layout Design: Rules, Factors, Considerations

Source: DDR Memory Layout Design: Rules, Factors, Considerations

Common length matching route groups are:

Clock-to-Address/Command Group
Clock-to-Strobes Group
Strobe-to-Data Group

Clock-to-Address/Command Group:

The purpose of the Clock-to-Address/Command Group (abbreviated CLK/ADDR/CMD) is to match the overall length of the CLK signal(s) to all ADDR and CMD signals specified. Depending on memory type, density, and bank structure, this group can get complicated, as there may be a complex signal topology scheme, which must be followed.

Clock-to-Strobes Group (CLK/STB):

The requirement for the CLK/STB group is to match the overall total length of the CLK signal(s) to the Strobe and Data. This required group matching ties the CLK timing to the Data timing. The allowable matching tolerance is usually defined in the manufacturer’s data sheet.

Strobe-to-Data Group (STB/Data):

The final group—STB/Data—should match the STB signal(s) to the individual Data bit signals. Since the number of signals that a Data group can contain may be large, the Data group is generally broken into “Data Byte Lanes.” Each lane contains eight Data bits, plus one Data mask, and one STB, and all signals in this group must be length matched to specification.

Layout Strategy: (Suggested sequence of work)

Refer to applicable design guides for the memory controller.

Consider the IC package pin length data for accurate length matching.

Determine which pins can be swapped to simplify and optimize routing.

VREF trace width ~20mil.

Determine CK to DQSx skew and route path for Diff Pair DQSx.

Because Differential Pairs i.e. DQSx, CLK and VREF tracks require wider paths, they should be routed first. Keep in mind that all other signals in the data lanes or address /command bus will be matched length to the respective data strobe or clock.

Route data lanes, using only 2 vias per path and keep data lanes on same layer if possible. If it is not possible consider the flight time (Tpd) for each used layer and use the same number of vias in each path. Data lanes are always point to point, unlike address / command lines data lanes are not branch or flyby routed.

For high-speed memory data lanes consider, Consider layer usage to minimize Via Stubs. Data rate is 2x faster than clock because data is latched on both rising and trailing clock edges.

Route address / command. Using only 2 vias per path and layers with similar flight times. If signals on the layers have significantly different flight times you should analyze or simulate the design. Use appropriate branch, flyby or clam shell routing for address buses.

For flyby typologies and depending on the design tool used you may want to route each memory chip in sequence, i.e. finish routing the first chip and length matching the signals in the address / command bus before routing the next chip. This technique can be used with tools that report the total routed length along the path. Higher end tools include accurate pin to pin length data.

For a two chip DDR4 design use four inner layer signal layers alternating the layer usage across the two chips.

Place termination resistors ~1/2 inch or less beyond the last memory chip. Distribute decoupling capacitors among the termination resistors, use one capacitor for every four resistors.

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