Xilinx Spartan-6 FPGA DDR3

• White Paper: Xilinx Spartan®-6 FPGA DDR3 Signal Integrity Analysis and PCB Layout Guidelines

Power Plane Resonance

Power Plane Resonance: Dr. Howard Johnson 1998

A bit dated (1998) but still relevant.

'via Blog this'

Analyzing Power Integrity Issues from Power Plane Interactions

"When a printed circuit board (PCB) includes a power plane that is near to signal traces or other power planes, there is a significant risk of energy transfer between parts of the system. Not only does this coupling lead to power switching noise being transferred into data signals, it also means that power supply systems may demonstrate additional resonances that are not seen in the individual components. This can affect the power integrity of the PCB and may reduce its speed or reliability. This paper will explore some of the potential power integrity issues that can affect a PCB and explain how simulation can be used to help reduce these effects."

Source: Analyzing Power Integrity Issues from Power Plane Interactions - White Paper

'via Blog this'

PDN - Calculate Target Impedance

Calculate Target Impedance

click on image to view

Using Saturn PCB Toolkit

That's it !

Reduce Anti-Resonance in Decoupling Caps

The anti-resonance occurs at a frequency when one capacitor is still capacitive, while another has become inductive. 

Source: Take steps to reduce antiresonance in decoupling | EDN:

And 

Murata’s New ESR Capacitors Tackle Anti-Resonance

'via Blog this'

PDN Tool | Free Tool to Optimize Bypass Capacitors

PDN Tool | Free Tool to Optimize Bypass Capacitors:

'via Blog this'

PCB and ESR subtleties in switching regulator and LDO designs | EDN

PCB and ESR subtleties in switching regulator and LDO designs | EDN: 

'via Blog this'

Evaluating DC-DC Converters

Evaluating DC-DC Converters and PDNwith the E5061B LF-RF Network Analyzer

'via Blog this'

PDNDesigner | Giga Hertz Technology

PDNDesigner | Giga Hertz Technology:

30 Day Free Trial 

'via Blog this'

Zed Board Power Decoupling Scheme

Research Links:

Zedboard Decoupling

Does the Zedboard bypass scheme make sense?

Bypass cap location is irrelevant?

How much Bypass does the Zynq have On-chip?

Are there flaws in the reasoning behind the Zedboard bypass scheme?

Measuring Bypass Capacitors on a Populated Board

PDN - Target impedance

"One of the more common design techniques for power distribution networks (PDN) is the determination of the peak impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. "

Full Article:
Target impedance based solutions for PDN may not provide realistic assessment | EDN: 

How-to-make-higher-voltage-power-distribution-network-measurements


PDN Tool V1:

Here is nice Java Script tool from EE- Training for PDN Calculations

'via Blog this'