PCB Designer: Stackups

Showing posts with label Stackups. Show all posts

Tuesday, May 7, 2024

PCB Stackup Designer - Sierra Circuits

Sierra Circuits - Online Stackup Designer

Stackup Designer | Sierra Circuits

Bandwidth, Rise time & Critical Length Calculator | Sierra Circuits

Saturday, September 16, 2023

Megtron - Panasonic

https://industrial.panasonic.com/ww/products/pt/megtron

Sunday, June 20, 2021

Formal Stackups are Designed by Fabricators

Formal Stackups are designed by Fabricators, NOT PCB designers.

PCB designers create requirements that the fabricators use to design the stackup.

Fabricators can select from a wide variety of materials, like . . .

Cores, PrePregs, Glass Weaves and Resin Contents

Fabricators make material choices that meet their manufacturing processes needs.

Here's what PCB Designers can and SHOULD do:

When requesting a stackup let the fabricator know if the design is using VIPPO or heavy copper.

Let the fabricator know if you have CAF concerns or if you need high speed glass.

For High-speed and RF you may want to specify materials that have low Df specs.

Specify the Desired Overall Board Thickness +/- 10%

PCB Designers Create Fab Drawings with Controlled Requirements, like . . .

50 OHM 0.005" TRACES L1 REF TO L2 +/- 10%

50 OHM 0.004" TRACES L3 REF TO L2 AND L4 +/- 10%

100 DIFF 0.004" TRACES, PITCH 12 (GAP + WIDTH = PITCH)

RF TRACES

50 RB/CPW 0.020" TRACES, PITCH 30 L1 REF TO L4 +/- 10%

Designers can add notes to the project Fab Drawing, like . . .

Reference Only: Refer to Fabricator Stackup.

Customer Approval is Required for Stackup Changes.

The requirements in the fab drawing will drive the stackup designed by the fabricator.

PCB Designers can use various calculators to approximate the stackup, however the final stackup needs to come from the fabricator that is fabricating the PCB and performing TDR tests for the controlled impedances.

To expedite designs and minimize layout rework a formal stackup should be obtained from the preferred fabricator to optimize controlled impedances.

Length matching may also need to be reworked if it is done before a formal (fabricator) stackup is obtained.

Summary: Working with a fabricator sooner, rather than later is highly recommended.

Abbreviations:

CAF is Cathodic Anodic Filament

Df is Dissipation Factor ( signal attention at higher frequencies )

VIPPO is Via In Pad Plated Over

That's it !

Wednesday, December 16, 2020

RF Design Reuse - Stackup Comments

For RF design reuse the 50 ohm trace width, distance to RF reference plane and PCB material need to be tightly constrained.

A well designed RF circuit can be moved to another PCB stackup provided the RF trace widths and dielectric thickness to the RF reference plane are nearly the same.

RF matching work will be needed to optimize RF performance after changing stackups.

The Dielectric Constant (Dk or Er) is determined by the ratio of resin to glass.

The Dk of the material and distance to the reference plane determines the trace widths of the controlled impedances.

Dissipation Factor (Df or loss tangent). Low Df materials are preferred for RF performance.

Layer stackup considerations may include high-speed traces on outer layers which will require a thinner dielectric (~2.5mil) between L1 to L2. A thicker dielectric (~3mil) can be used with a few impedance discontinuities and imperfections, i.e. trace width neck downs on the outer layers.

Vias in Pad Plated Over (VIPPO). RF designers appreciate VIPPO because it reduces the parasitics associated with vias and traces connected to RF components.

For fine pitch components in the design use thru-hole vias with a minimum size of 0.2mm / 0.45mm (drill / pads) or 8/18mil and very sparingly use 0.2mm / 0.4mm (8/16) where needed.

Use 10/22mil vias where possible. Vias hole sizes should be 15mil or smaller to accommodate non-conductive fill and plated over vias ( VIPPO).

For high-speed designs consider using blind vias or back drilling a few thru-hole vias to reduce stub lengths.

Blind vias may be less likely than thru-hole vias to experience via barrel fractures from repetitive thermal expansion in the Z axis, Blind vias can also be useful where RF isolation is needed.

That it !

Monday, June 8, 2020

Stackup Request - Designer to Customer

We need to work with your preferred fabricator to create formal stackups.

The overall board thickness, choice of materials (glass and resin) and the material Dk (dielectric constant) will determine precise trace widths and spaces for controlled impedance.

The ideal material for high-speed designs will have low a Df (dissipation factor) to minimize signal attenuation. The length of the traces should be considered when selecting the materials. If traces are short and wide then Df will not be a significant factor. Low Df material is typically used on a high speed back planes and RF designs. Note low Df materials are more expensive.

To maintain manufacturable trace widths as layer count increases where overall board thickness is ~80 mils or less the Dk needs to be lower than what is typically found on popular FR4 materials like 370HR. FR408HR and GETEK are a popular choices for low Dk materials.

Fabricators prefer plated holes (vias) sized with 10:1 or less aspect ratio. Where the aspect ratio is the overall board thickness divided by the drill hole size.

Note drill/pad sizes 8/20mil (0.2/0.5mm) are needed to allow for routing diff pairs or two signal traces between the vias under 1mm pitch BGA and routing one trace between the vias 0.8mm pitch connectors.

Please provide a email contact for your preferred fabricator. We can work with your fabricator to design formal stackups and keep you in the loop (on the email threads).

That's it !