DDR Memories Comparison and Overview|Freescale

DDR Memories Comparison and Overview|Freescale:

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Validation of DDR2/3 Designs

Validation of DDR2/3 Designs Agilent

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DDR Memory Layout Design: Rules, Factors, Considerations

Source: DDR Memory Layout Design: Rules, Factors, Considerations

Common length matching route groups are:

• Clock-to-Address/Command Group
• Clock-to-Strobes Group
• Strobe-to-Data Group

 Clock-to-Address/Command Group:

The purpose of the Clock-to-Address/Command Group (abbreviated CLK/ADDR/CMD) is to match the overall length of the CLK signal(s) to all ADDR and CMD signals specified. Depending on memory type, density, and bank structure, this group can get complicated, as there may be a complex signal topology scheme, which must be followed.

 Clock-to-Strobes Group (CLK/STB):

The requirement for the CLK/STB group is to match the overall total length of the CLK signal(s) to the Strobe and Data. This required group matching ties the CLK timing to the Data timing. The allowable matching tolerance is usually defined in the manufacturer’s data sheet.

 Strobe-to-Data Group (STB/Data):

The final group—STB/Data—should match the STB signal(s) to the individual Data bit signals. Since the number of signals that a Data group can contain may be large, the Data group is generally broken into “Data Byte Lanes.” Each lane contains eight Data bits, plus one Data mask, and one STB, and all signals in this group must be length matched to specification.

Layout Strategy:  (Suggested sequence of work)

Refer to applicable design guides for the memory controller.

Consider the IC package pin length data for accurate length matching.

Determine which pins can be swapped to simplify and optimize routing.

VREF trace width ~20mil.

Determine CK to DQSx skew and route path for Diff Pair DQSx.  

Because Differential Pairs i.e. DQSx, CLK and VREF tracks require wider paths, they should be routed first.  Keep in mind that all other signals in the data lanes or address /command bus will be matched length to the respective data strobe or clock.

Route data lanes, using only 2 vias per path and keep data lanes on same layer if possible. If it is not possible consider the flight time (Tpd) for each used layer and use the same number of vias in each path.  Data lanes are always point to point, unlike address / command lines data lanes are not branch or flyby routed.

For high-speed memory data lanes consider, Consider layer usage to minimize Via Stubs. Data rate is 2x faster than clock because data is latched on both rising and trailing clock edges.

Route address / command. Using only 2 vias per path and layers with similar flight times. If signals on the layers have significantly different flight times you should analyze or simulate the design.  Use appropriate branch, flyby or clam shell routing for address buses.

For flyby typologies and depending on the design tool used you may want to route each memory chip in sequence, i.e. finish routing the first chip and length matching the signals in the address / command bus before routing the next chip. This technique can be used with tools that report the total routed length along the path. Higher end tools include accurate pin to pin length data.

For a two chip DDR4 design use four inner layer signal layers alternating the layer usage across the two chips.

Place termination resistors ~1/2 inch or less beyond the last memory chip.  Distribute decoupling capacitors among the termination resistors, use one capacitor for every four resistors.

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Length Matching for High-Speed Differential Pairs

Tpd - One of my favorite topics.

http://pcdandf.com/cms/images/stories/mag/0502/0502strategies.pdf


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Propagation Delay - Tpd

Lately I have been routing DDR3 designs and I'm keenly aware of Tpd. Why ?

Tpd = 1/(11.8/(SQRT(Keff)))*1000

Where Keff = the effective dielectric constant of the material surrounding the trace.

Let's say you have routed a portion of a DDR Data signal as a 50 Ohm 1 inch track on an outer layer, note Tpd ~ 139pSec per inch for a 50 Ohm microstrip.

And for the same net you have routed another 1 inch of track as 50 Ohm stripline on an inner layer, note Tpd = ~ 170pSec per inch for a 50 Ohm stripline.

Not counting for the Via length, the two inches of net routed as described above are 139pS + 170pS, which equals 309pSec.

As you can see if we are routing high speed signals with matched trace lengths then it matters what layer the traces are on.

Example:
2 inches of 50 Ohm microstrip = 2 x 139pS = 278pS
2 inches of 50 Ohm Stripline = 2 x 170pS = 340pS

That's big timing difference in terms of pSecs.  340pS - 278pS = 62pS

62pS would equal ~372mils of trace length.

Knowing Tpd and the length of your traces is critical for high speed designs.

Because signal velocity is FASTER FOR OUTER LAYER TRACES THAN FOR INNER LAYER TRACES, propagation delay is smaller for the outer layer.

There are fewer Tpd calculators available for differential pairs.  Differential pairs are slightly faster than single trace stripline conductors.  For a typical 100 Ohm differential pair Tpd ~ 155pSec per inch.

Clock skew needs to be considered in DDR3 length matching to the data lanes, therefore knowing the Tpd for the differential clock pairs is important.

Matched Timing:

To avoid timing mismatches designers often route data lanes on the same layers using equal trace lengths and geometry on each layer that the signals traverse.

Use the same number of vias in each signal routed. 

You may need to adjust the trace length for the differential pairs to match timing to the single-ended microstrip and stripline traces.

Tpd is propagation delay and V (velocity) is the reciprocal of Tpd. 

Example: if Tpd = 139pS/inch then V = 1/139 = 0.00719 inches per pSec.
Example: if Tpd = 170pS/inch then V = 1/170 = 0.00588 inches per pSec.

Rule of thumb: 
Typical FR4 material 6mils of trace is ~ 1 pSec.

That's it.

Analyzing DDR2/3/4 with Hyperlynx: - Mentor Graphics

On Demand Webinar

Analyzing DDR2/3/4 Memory Interfaces: Guarantee Your Margins Before You Build and Ship Boards - Mentor Graphics:

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DDRx Speed

Clock Rate (MHz) is the reciprocal of Clock Cycle (nSec)

and 

Clock Cycle (nSec) is the reciprocal of Clock Rate (MHz)

DDR is defined as double data rate, which means the data bits are clocked on both the rising and falling edges of the clock. 

DDR3 with Clock Rate of 800MHz would have a Data Rate of 1600.

Example of manufacturer specs.

DDR2 and DDR3 SDRAM Board Design - Altera

http://www.altera.com/literature/hb/external-memory/emi_plan_board_ddr2.pdf

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DDRx Design Topologies

Source: TI App Note SPRAB11A

Typical DDR2 Balanced "T" Topology

Typical DDR3 Fly By Topology

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Altera High Speed - Board Design Resource Center

Board Design Resource Center