High-Speed Interface Layout Guidelines - TI

High-Speed Interface Layout Guidelines (Rev. J) - Texas Instruments

Per Gemini - Google AI

There are actually two main reasons why differential signals are not always preferred for routing on the outer layers of a printed circuit board (PCB), and it has to do with the type of transmission line formed:

Microstrip vs. Stripline:

Outer layers create microstrip transmission lines, where the signal trace has a reference plane on one side (usually a power plane) and air on the other.

Differential signals rely on a consistent and symmetrical environment for optimal performance. Microstrip, due to its air exposure, introduces an asymmetry that can affect the common-mode vs. differential-mode propagation characteristics.

Controlled Impedance:

Precise control over the impedance of the transmission line is crucial for high-speed differential signals. Microstrip's impedance is more sensitive to variations in manufacturing tolerances compared to stripline.

However, there are some advantages to routing differential signals on outer layers:

Slightly Faster Signal Propagation:

Outer layers have a lower effective dielectric constant due to the presence of air. This can lead to marginally faster signal travel compared to inner layer routing.

Easier Access for Controlled-Impedance Routing Techniques:

The outer layers are more accessible for adding solder masks or prepreg layers to adjust the trace width and spacing, allowing for finer control over impedance.

In conclusion, the decision to route differential signals on outer layers depends on the specific application's priorities. For high-performance applications where signal integrity is paramount, stripline routing on inner layers with a controlled and symmetrical environment is usually preferred. However, for lower-speed applications where manufacturability and ease of access are important, outer layer routing with microstrip can be a viable option, considering the trade-offs mentioned above.

That's it !

Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission - Altera

Altera AppNote AN672 was recently updated. This app note is perfect for anyone who is on the high speed learning curve.

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High-speed PCB Primer for SATA, PCIe, USB 2.0 and HDMI - YouTube

High-speed PCB Primer for SATA, PCIe, USB 2.0 and HDMI - YouTube:

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Xilinx Spartan-6 FPGA DDR3

• White Paper: Xilinx Spartan®-6 FPGA DDR3 Signal Integrity Analysis and PCB Layout Guidelines

Getting EMC design right – First time | EDN

Getting EMC design right – First time, Part 1: Grounding & planes
Getting EMC design right – First time, Part 2: Decoupling, PDN impedance
Getting EMC design right – First time, Part 3: High-speed signals & Impedance 
Getting EMC design right – First time, Part 4: Terminations & Parts placement 
Getting EMC design right – First time, Part 5: Routing 
Getting EMC design right – First time, Part 6: Signal Timing
Getting EMC design right – First time, Part 7: Crosstalk

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Base Materials for High Speed and High Frequency Boards

Base Materials for High Speed, High Frequency PC Boards. 

By: Rick Hartley, March 2002, Published in PCB & A 

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Design Guidelines for Highspeed - Gbps Data Rates

Loss Tangent (Dissipation Factor) of PCB Materials

Source: Altera App Note 672

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High Speed Analog Design and Application Seminar

Section 1.  Understanding Voltage Feedback and Current Feedback Amplifiers
Section 2.  Useful Things to Know About Amplifiers
Section 3.  Useful Things to Know about A/D Converters
Section 4.  Selecting the right high-speed Amplifier
Section 5.  High-speed layout
Section 6.  Application design

Source: Texas Instruments

High Speed Board Layout Guidelines - Altera

click on image to see Altera App 224

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PCBDESIGN007 Isola's I-Speed Endorsed as Laminate Choice for PCBs

"I-Speed has been endorsed by two leading companies as the laminate of choice for PCBs using sequential lamination technology, requiring high conductive anodic filament (CAF) reliability and improved, cost effective signal integrity."

Source:
PCBDESIGN007 Isola's I-Speed Endorsed as Laminate Choice for PCBs:

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Propagation Delay - Tpd

Lately I have been routing DDR3 designs and I'm keenly aware of Tpd. Why ?

Tpd = 1/(11.8/(SQRT(Keff)))*1000

Where Keff = the effective dielectric constant of the material surrounding the trace.

Let's say you have routed a portion of a DDR Data signal as a 50 Ohm 1 inch track on an outer layer, note Tpd ~ 139pSec per inch for a 50 Ohm microstrip.

And for the same net you have routed another 1 inch of track as 50 Ohm stripline on an inner layer, note Tpd = ~ 170pSec per inch for a 50 Ohm stripline.

Not counting for the Via length, the two inches of net routed as described above are 139pS + 170pS, which equals 309pSec.

As you can see if we are routing high speed signals with matched trace lengths then it matters what layer the traces are on.

Example:
2 inches of 50 Ohm microstrip = 2 x 139pS = 278pS
2 inches of 50 Ohm Stripline = 2 x 170pS = 340pS

That's big timing difference in terms of pSecs.  340pS - 278pS = 62pS

62pS would equal ~372mils of trace length.

Knowing Tpd and the length of your traces is critical for high speed designs.

Because signal velocity is FASTER FOR OUTER LAYER TRACES THAN FOR INNER LAYER TRACES, propagation delay is smaller for the outer layer.

There are fewer Tpd calculators available for differential pairs.  Differential pairs are slightly faster than single trace stripline conductors.  For a typical 100 Ohm differential pair Tpd ~ 155pSec per inch.

Clock skew needs to be considered in DDR3 length matching to the data lanes, therefore knowing the Tpd for the differential clock pairs is important.

Matched Timing:

To avoid timing mismatches designers often route data lanes on the same layers using equal trace lengths and geometry on each layer that the signals traverse.

Use the same number of vias in each signal routed. 

You may need to adjust the trace length for the differential pairs to match timing to the single-ended microstrip and stripline traces.

Tpd is propagation delay and V (velocity) is the reciprocal of Tpd. 

Example: if Tpd = 139pS/inch then V = 1/139 = 0.00719 inches per pSec.
Example: if Tpd = 170pS/inch then V = 1/170 = 0.00588 inches per pSec.

Rule of thumb: 
Typical FR4 material 6mils of trace is ~ 1 pSec.

That's it.

High Speed Via - EE Training

High Speed Via:

Nice article about creating 50 Ohms vias.


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DDR2 and DDR3 SDRAM Board Design - Altera

http://www.altera.com/literature/hb/external-memory/emi_plan_board_ddr2.pdf

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Length Matching for High-Speed Differential Pairs

Using loops and serpentines to eliminate imbalance in differential pairs.

Author: Abe Riazi

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Via Optimization Techniques for High-Speed Channel Designs

http://www.altera.com/literature/an/an529.pdf


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In-Circuit Design - PCB Design and Simulation Services

In-Circuit Design - Barry Olney

In-Circuit Design - PCB Design and Simulation Services. Differential Impedance Calculator, Stackup Planner, Transmission line, stripline, microstrip, DDR2 Signal Integrity, Crosstalk and EMC .... Analysis, Impedance, Altium Designer, Protel, PCAD, OrCAD Translators, PCB Design Layout, PCB Design Services.

Generalized I/O Timing Analysis - Part 1

Generalized I/O Timing Analysis - Part 1

www.icd.com.au/

ICD has some excellent Design Notes an Tips for High speed Designers

http://www.icd.com.au/

DDRx_AN2010.pdf

DDRx_AN2010.pdf (application/pdf Object)