si-list Mailing List Archive: Signal Integrity
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Showing posts with label Signal Integrity. Show all posts
Showing posts with label Signal Integrity. Show all posts
Sunday, November 1, 2015
Friday, February 20, 2015
Sunday, August 31, 2014
Sunday, August 24, 2014
Wednesday, August 20, 2014
Samtec Signal Integrity Book
Connector Pin Mapping
"By assigning pins between signals as return paths (grounds), unwanted coupling between signal pins can be minimized. For high speed applications a 1:1 signal to ground ratio is typically optimal. Pin mapping for SE applications would then be S-G-S-G, while DP applications would use DP-G-DP-G.
These pin assignments provide a good performance versus density trade-off. Of course, more return paths could be added between signals to increase isolation for applications where crosstalk must be extremely low. However, this greatly reduces signal density of the interconnect."
Source: Samtec Signal Integrity Book
"By assigning pins between signals as return paths (grounds), unwanted coupling between signal pins can be minimized. For high speed applications a 1:1 signal to ground ratio is typically optimal. Pin mapping for SE applications would then be S-G-S-G, while DP applications would use DP-G-DP-G.
These pin assignments provide a good performance versus density trade-off. Of course, more return paths could be added between signals to increase isolation for applications where crosstalk must be extremely low. However, this greatly reduces signal density of the interconnect."
Source: Samtec Signal Integrity Book
Monday, August 18, 2014
Signal Integrity - Guidelines
Stripline traces passing over a split plane should be at least four times farther from the signal than the reference plane. Source: Eric Bogatin
If a signal changes reference planes when passing through a via, add an adjacent ground via.
Source : Signal Consulting Inc. Dr. Johnson
Use a capacitor to AC couple the return path when reference planes are at different potentials.
Source: TDK Outline of EMC Design Methods
This article compares the propagation delay (tpd) for serpentine, spiral, and straight traces.
The results show that a signal will travel faster in a microstrip serpentine trace compared to a straight trace of the same length. And the stripline serpentine trace will lag the straight trace.
Source: A New Slant on Matched-Length Routing - Barry Olney
Serpentine Gaps should be 3 x height to nearest reference plane.
When a design requires equal-length traces between the source and multiple loads, you can bend some traces to match trace lengths (see Figure 11–20). However, improper trace bending affects signal integrity and propagation delay.
To minimize crosstalk, ensure that S ≥ 3 × H, where S is the spacing between the parallel sections and H is the height of the signal trace above the reference ground plane.
Click on images to view
Differential Pairs
D = distance between two differential pair signals; W = width of a trace in a differential pair; S = distance between the traces in a differential pair; and H = dielectric height above the group plane.
If a signal changes reference planes when passing through a via, add an adjacent ground via.
Source : Signal Consulting Inc. Dr. Johnson
Use a capacitor to AC couple the return path when reference planes are at different potentials.
Source: TDK Outline of EMC Design Methods
This article compares the propagation delay (tpd) for serpentine, spiral, and straight traces.
The results show that a signal will travel faster in a microstrip serpentine trace compared to a straight trace of the same length. And the stripline serpentine trace will lag the straight trace.
Source: A New Slant on Matched-Length Routing - Barry Olney
Serpentine Gaps should be 3 x height to nearest reference plane.
When a design requires equal-length traces between the source and multiple loads, you can bend some traces to match trace lengths (see Figure 11–20). However, improper trace bending affects signal integrity and propagation delay.
To minimize crosstalk, ensure that S ≥ 3 × H, where S is the spacing between the parallel sections and H is the height of the signal trace above the reference ground plane.
Click on images to view
Differential Pairs
D = distance between two differential pair signals; W = width of a trace in a differential pair; S = distance between the traces in a differential pair; and H = dielectric height above the group plane.
- Ensure that D > 2S to minimize the crosstalk between the two differential pairs.
- Place the differential traces S = 3H as they leave the device to minimize reflection noise.
- Keep the length of the two differential traces the same to minimize the skew and phase difference.
- Avoid using multiple vias because they can cause impedance mismatch and inductance.
Molex Pin Map Configurator
Molex Pin Map Configurator:
Signal Integrity Support from Molex for Backplane Connectors, nice !
Video Link
'via Blog this'
Signal Integrity Support from Molex for Backplane Connectors, nice !
Video Link
'via Blog this'
Friday, August 1, 2014
Sunday, May 11, 2014
Tuesday, October 1, 2013
Wednesday, September 4, 2013
Monday, June 24, 2013
Friday, December 28, 2012
Right the First Time - Lee Ritchey
Right the first is an excellent PCB Design resource authored by Lee Ritchey.
Lee has made this book available for free download: Right the First Time:
Lee has made this book available for free download: Right the First Time:
Saturday, November 10, 2012
Sunday, November 4, 2012
In-Circuit Design - PCB Design and Simulation Services
In-Circuit Design - Barry Olney
In-Circuit Design - PCB Design and Simulation Services. Differential Impedance Calculator, Stackup Planner, Transmission line, stripline, microstrip, DDR2 Signal Integrity, Crosstalk and EMC .... Analysis, Impedance, Altium Designer, Protel, PCAD, OrCAD Translators, PCB Design Layout, PCB Design Services.
In-Circuit Design - PCB Design and Simulation Services. Differential Impedance Calculator, Stackup Planner, Transmission line, stripline, microstrip, DDR2 Signal Integrity, Crosstalk and EMC .... Analysis, Impedance, Altium Designer, Protel, PCAD, OrCAD Translators, PCB Design Layout, PCB Design Services.
Tuesday, September 25, 2012
Source Termination Resistor Location
Source Termination Resistor Location - David Norte
Source Termination Resistor Location And Its Impact On The Signal Integrity Of High Impedance Loads.
Source Termination Resistor Location And Its Impact On The Signal Integrity Of High Impedance Loads.
Transmission Lines and Terminations
AN246 Transmission lines and terminations with Philips Advanced Logic families
Critical Line Length per Logic Family
Critical Line Length per Logic Family
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