DC Bias Effects on X5R & X7R Capacitors

If this capacitor was used as a bypass capacitor with 15V applied, the effective capacitance is not 4.7uF, but only 20% of 4.7uF, or 0.94uF.

See the TDK video link below for the explanation:

https://product.tdk.com/info/en/contact/faq/faq_detail_D/1432616875432.html

Related Links:

Operating Above Resonance - Dr Howard Johnson
EEVblog #626 - Ceramic Capacitor Voltage Dependency - YouTube

That's it !

Standard Resistor Value Calculator - Daycounter Inc

Click on me to Open the Calculator



Source:  Daycounter Inc

DPPM / FIT / MTBF Estimator - Texas Instruments

Source: Texas Instruments DPPM / FIT / MTBF Estimator

IPC Class 2 VS Class 3: The Different Design Rules

click on image to view

Source: IPC Class 2 VS Class 3: The Different Design Rules | Sierra Circuits Blog

Randy's Comments:

IPC specs do not dictate the pad size. It's all about the finished minimum annular ring.

The IPC criteria is 2 mil finished annular ring on external layers and 1 mil minimum on the internal layers. Class 3 pad sizes > drill + 12mil are imposed by fabricators who have > 4 mil layer to layer tolerances.  

It comes down to fabricators capability and process tolerances.  Smaller pads can be used if the fabricator has tight layer to layer tolerances.  

Just be aware that tighter (smaller) tolerances will impact yields and the costs will be passed to the customer.

The other noteworthy Class 3 requirement for vias is the via barrel wall plating must have an average minimum thickness of 1 mil.  Stringent class 3 fab notes will specify an absolute minimum thickness for the barrel plating.

That's it !

Estimating Ground Bounce

click on image to view

Source:
How to estimate ground bounce in a connector- Rule of Thumb #8 - EDN

That's it !

PCB Signal Integrity: Understand Coupling - YouTube

PCB Signal Integrity: Understand Coupling - YouTube:

Home - GigaTest Labs

Home - GigaTest Labs: "The Industry's leading Signal Integrity Company. Serving the Electronics Industry with Engineering Excellence."

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Using Remote Sensing - Vicor

Source:

Using Remote Sensing to Ensure Accurate Point of Load Voltage Control | VicorPowerBlog: 

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KwickFit - Fixed Size PCB Array Calculator

Fixed Size PCB Array Calculator:

click image to view

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Calculate Distributed Line Length

Distributed element wavelengths occur at fractional wavelengths.

1/4 for Digital Paths
1/12 for RF Paths
1/16 for Analog Paths

Use the Saturn PCB Toolkit v7.05 to calculate lumped / distributed wavelengths.

Note that 1/Time = Freq and 1/Freq = Time, they are reciprocals.

In the Saturn PCB Toolkit select the Wavelength Calculator tab.

Example: 

Select the Period to enter the edge rate transition time. 

Enter 1nS for the Risetime period. (10% to 90%)
Enter the Er Eff (effective Er (Dk) Dielectric Constant.
Set Wavelength Divide to 1/4 Wave Length.

click on image to view

As shown above the distributed 1/4 wavelength = 1.46 inches for a rise time of 1 nS.

Paths shorter than this length are lumped lengths and longer lengths are distributed length paths. Distributed lengths should be impedance controlled paths.

Something for the RF Geeks:  Quarter Wave Tricks

Something for Everyone: Admiral Grace Hopper Explains the Nanosecond

Who is Grace Hopper? - YouTube

That's it !

Rounded Rectangle Pad Shape - PCB Libraries Forum

Illustrations of solder joints of rectangle pads, note  there is no solder in the corners after reflow.



PCB manufacturer's have long recommended Rounded Corner SMD pad shape for several reasons. Better stencil release and paste mask stencil apertures are normally corner radius.

Source: Rounded Rectangle Pad Shape - PCB Libraries Forum:

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PCB2DAY: What Will Rick Hartley Teach You?

PCB2DAY: What Will Rick Hartley Teach You? | Sierra Circuits Blog:

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Circuit Board Layout for EMC: Example 1 - YouTube

Circuit Board Layout for EMC: Example 1 - YouTube:

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Layout Tips for Radiated EMI Reduction in Your Switching Power Supplies - YouTube

Layout Tips for Radiated EMI Reduction in Your Designs - YouTube:

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Switching Power Supply PCB Layout Seminar

Source: Switching Power Supply PCB Layout Seminar: Optimum

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A Manual Tuning Method for Coupled Cavity Filters_百度文库

A Manual Tuning Method for Coupled Cavity Filters_百度文库: "A Manual Tuning Method for Coupled Cavity Filters"

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Semiconductor Engineering .:. The Road To Autonomy

Semiconductor Engineering .:. The Road To Autonomy:

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Via In Pad - Conductive Fill or Non-Conductive Fill?

Very few fabricators offer conductive fill because the Vias may break (fracture) during lead free reflow (oven soldering) due to thermal coefficient differences between the conductive fill and the surrounding PCB materials.

Suggested reading: 

http://www.4pcb.com/TechTalk_Conductive_or_Non-conductive_VIP_Fill.pdf

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Convert 140 pSec/inch to pSec/cm - Google Search

Convert 140 pSec/inch to pSec/cm - Google Search:

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I-Connect007 :: Books

I-Connect007 :: Books:

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Common PCB Design Issues and Reasons for Circuit Board Failure

Common PCB Design Issues and Reasons for Circuit Board Failure:

Acid Traps

Plating Voids
Slivers
Insufficient Copper-to-Edge Clearance

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