Wednesday, February 23, 2022
Friday, December 31, 2021
Thursday, December 16, 2021
Friday, December 3, 2021
Wednesday, December 1, 2021
Electronic Tutorials
If you are looking for some good Electronic educational material try . . .
Electronics Tutorials
That's it !
Monday, November 29, 2021
Ethernet Design Guidelines
"The total length of each MII trace should be less than 6 inches, or 6000 mils. The traces should be length matched within 20 mils for 1G transmissions and length-matched within 50 mils for 100M or 10M transmissions. RX traces must be length-matched to the other RX traces, and TX traces must be length-matched to the other TX traces. The number of vias and stubs on the MII traces should be kept to a minimum."
Magnetic Isolation No metal should be under the magnetics on any layer. If metal is needed under the magnetics, it must be separated by a ground plane at the least. Metal under the RJ45 connector with integrated magnetic is allowed.
Source Texas Instruments:
Chassis / GND for RJ45 with Integrated Magnetics 
Source NXP APP Note 4215:
That's it !
Wednesday, October 20, 2021
Vias are critical to PCB functionality as the conduit for transferring signals between layers. Vias can remain open, tented over with soldermask or filled solid with either non-conductive or conductive material.
Conductively filled vias add capacity to the design, and using copper to fill the vias adds some benefits that other conductive material does not, including thermal and electrical conductivity. The high thermal conductivity of copper-filled vias provides an advantage in high heat applications and the added electrical conductivity provides superior current-carrying capability in high voltage applications.
ASC’s John Bushie takes us through the complex manufacturing process in this month’s video.
Subscribe to:
Posts (Atom)