DR1040 Series
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Inductors generate magnetic fields which can couple to adjacent circuitry and induce unwanted current and voltages.
That's it !
Friday, January 4, 2019
Inductors - Best Practices
Per the manufacturer datasheet your should NOT route traces or place vias under inductors.
DR1040 Series
click on image to view
Inductors generate magnetic fields which can couple to adjacent circuitry and induce unwanted current and voltages.
That's it !
DR1040 Series
click on image to view
Inductors generate magnetic fields which can couple to adjacent circuitry and induce unwanted current and voltages.
That's it !
Tuesday, October 23, 2018
DC Bias Effects on X5R & X7R Capacitors
If this capacitor was used as a bypass capacitor with 15V applied, the effective capacitance is not 4.7uF, but only 20% of 4.7uF, or 0.94uF.
See the TDK video link below for the explanation:
Related Links:
Operating Above Resonance - Dr Howard Johnson
EEVblog #626 - Ceramic Capacitor Voltage Dependency - YouTube
EEVblog #626 - Ceramic Capacitor Voltage Dependency - YouTube
That's it !
Wednesday, August 15, 2018
Saturday, July 21, 2018
Thursday, July 5, 2018
IPC Class 2 VS Class 3: The Different Design Rules
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Randy's Comments:
IPC specs do not dictate the pad size. It's all about the finished minimum annular ring.
The IPC criteria is 2 mil finished annular ring on external layers and 1 mil minimum on the internal layers. Class 3 pad sizes > drill + 12mil are imposed by fabricators who have > 4 mil layer to layer tolerances.
It comes down to fabricators capability and process tolerances. Smaller pads can be used if the fabricator has tight layer to layer tolerances.
Just be aware that tighter (smaller) tolerances will impact yields and the costs will be passed to the customer.
The other noteworthy Class 3 requirement for vias is the via barrel wall plating must have an average minimum thickness of 1 mil. Stringent class 3 fab notes will specify an absolute minimum thickness for the barrel plating.
That's it !
Monday, June 4, 2018
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