RF Design Reuse - Stackup Comments

For RF design reuse the 50 ohm trace width, distance to RF reference plane and PCB material need to be tightly constrained.

A well designed RF circuit can be moved to another PCB stackup provided the RF trace widths and dielectric thickness to the RF reference plane are nearly the same.  

RF matching work will be needed to optimize RF performance after changing stackups.

The Dielectric Constant (Dk or Er) is determined by the ratio of resin to glass.

The Dk of the material and distance to the reference plane determines the trace widths of the controlled impedances.

Dissipation Factor (Df or loss tangent). Low Df materials are preferred for RF performance.

Layer stackup considerations may include high-speed traces on outer layers which will require a thinner dielectric (~2.5mil) between L1 to L2.   A thicker dielectric (~3mil) can be used with a few impedance discontinuities and imperfections, i.e. trace width neck downs on the outer layers.

Vias in Pad Plated Over (VIPPO). RF designers appreciate VIPPO because it reduces the parasitics associated with vias and traces connected to RF components.

For fine pitch components in the design use thru-hole vias with a minimum size of 0.2mm / 0.45mm (drill / pads) or 8/18mil and very sparingly use 0.2mm / 0.4mm (8/16) where needed.

Use 10/22mil vias where possible.  Vias hole sizes should be 15mil or smaller to accommodate non-conductive fill and plated over vias ( VIPPO).

For high-speed designs consider using blind vias or back drilling a few thru-hole vias to reduce stub lengths. 

Blind vias may be less likely than thru-hole vias to experience via barrel fractures from repetitive thermal expansion in the Z axis,  Blind vias can also be useful where RF isolation is needed.

That it !