Better DFM for PCBs | Online Design For Manufacturability Check Tool:
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Tuesday, April 29, 2014
Tuesday, April 22, 2014
Transparent Via Design - Altera App Note 672
Transparent Via Design
Unless you are routing all transceiver channels with only microstrip traces on the top layer, you must use vias in the design to transition layers.
Unfortunately, the characteristic impedance of differential vias are lower than 100 Ω.
Generally it is in the range of 80 to 85 Ω. This impedance mismatch causes reflections that degrade the channel performance.
To better match the impedance of the via with the 100 Ω differential traces requires optimization techniques that minimize the parasitic capacitance (Cvia) and inductance (Lvia) of the via.
Tip: You can minimize Cvia using the following optimization techniques:
• Reduce the via capture pad size
• Eliminate all non-functional pads (NFP)
• Increase the via anti-pad size to 40 or 50 mils
Tip: You can minimize Lvia using the following optimization techniques:
• Eliminate and / or reduce via stubs
• Minimize via barrel length by routing the stripline traces near the outer layers.
• Use back drilling to minimize stub lengths.
Unless you are routing all transceiver channels with only microstrip traces on the top layer, you must use vias in the design to transition layers.
Unfortunately, the characteristic impedance of differential vias are lower than 100 Ω.
Generally it is in the range of 80 to 85 Ω. This impedance mismatch causes reflections that degrade the channel performance.
To better match the impedance of the via with the 100 Ω differential traces requires optimization techniques that minimize the parasitic capacitance (Cvia) and inductance (Lvia) of the via.
Tip: You can minimize Cvia using the following optimization techniques:
• Reduce the via capture pad size
• Eliminate all non-functional pads (NFP)
• Increase the via anti-pad size to 40 or 50 mils
Tip: You can minimize Lvia using the following optimization techniques:
• Eliminate and / or reduce via stubs
• Minimize via barrel length by routing the stripline traces near the outer layers.
• Use back drilling to minimize stub lengths.
Design Files for DDR3 240-pin Unbuffered DIMMs | JEDEC
Design Files for DDR3 240-pin Unbuffered DIMMs | JEDEC:
Registration is Free. Registered user can download DRR3 refernce designs.
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Registration is Free. Registered user can download DRR3 refernce designs.
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Soldermask 1:1
PCB Fabricators prefer the supplied soldermask and pad data to be 1:1.
When your PCB data goes to fabrication the soldermask layers are examined to determine if apertures have been modified (are not 1:1).
If your soldermask layers are not 1:1 then the fabricator will most likely NOT use your soldermask layers and they will try to use the solder paste layer to determine the actual pad sizes.
Fabricators shrink or expand the soldermask to optimize your design for best process yields.
Soldermask webs are removed if the soldermask features between pads of fine-pitch parts are less that 3 mils wide.
Gang mask is a term used to describe removing the soldermask between closed spaced pins.
Here is and example of a gang masked (SOIC, SOP) with a pin to pin pitch of 0.65mm.
Laser Direct Imaging (LDI) has greatly improved soldermask registration and reduced the soldermask swell requirements, which allow for wider soldermask webs around fine pitch parts.
I'm on a mission this month to determine what is currently the best practice for soldermask.
Should we provide 1:1 data to the fabricators ?
Research:
According to Tom H. who is the father and Champion of the IPC-7351 Land patterns:
Designers have two choices.
"Use a stock library with 1:1 scale masks and create fabrication and assembly notes for solder mask and paste mask adjustments".
"Create a custom library for a PCB layout and tell the manufacturer's not to touch (adjust) the Gerber data."
Source:
http://www.pcblibraries.com/forum/advice-for-solder-mask-paste-mask-layers_topic484.html
PCB Libraries has created a CAD tool neutral CAD Library Solution for Land Patterns.
http://www.pcblibraries.com/
By default this tool creates pads and soldermask 1:1.
When your PCB data goes to fabrication the soldermask layers are examined to determine if apertures have been modified (are not 1:1).
If your soldermask layers are not 1:1 then the fabricator will most likely NOT use your soldermask layers and they will try to use the solder paste layer to determine the actual pad sizes.
Fabricators shrink or expand the soldermask to optimize your design for best process yields.
Soldermask webs are removed if the soldermask features between pads of fine-pitch parts are less that 3 mils wide.
Gang mask is a term used to describe removing the soldermask between closed spaced pins.
Here is and example of a gang masked (SOIC, SOP) with a pin to pin pitch of 0.65mm.
Laser Direct Imaging (LDI) has greatly improved soldermask registration and reduced the soldermask swell requirements, which allow for wider soldermask webs around fine pitch parts.
I'm on a mission this month to determine what is currently the best practice for soldermask.
Should we provide 1:1 data to the fabricators ?
Research:
According to Tom H. who is the father and Champion of the IPC-7351 Land patterns:
Designers have two choices.
"Use a stock library with 1:1 scale masks and create fabrication and assembly notes for solder mask and paste mask adjustments".
"Create a custom library for a PCB layout and tell the manufacturer's not to touch (adjust) the Gerber data."
Source:
http://www.pcblibraries.com/forum/advice-for-solder-mask-paste-mask-layers_topic484.html
PCB Libraries has created a CAD tool neutral CAD Library Solution for Land Patterns.
http://www.pcblibraries.com/
By default this tool creates pads and soldermask 1:1.
Sunday, April 20, 2014
Thursday, April 17, 2014
Wednesday, April 16, 2014
Fabrication CAM Software - Genesis 2000
Genesis 2000 is by far the most popular and widely used front end CAM processing tool on the market today.
Supplying your design in formats that support by Genesis 2000 and life will be good.
Supported Formats Inputs
Supplying your design in formats that support by Genesis 2000 and life will be good.
Supported Formats Inputs
| "Genesis 2000 translators automatically identify all data formats, interpret the Gerber wheel, and convert incoming data to ODB++. Adaptive heuristic methodology is applied to maintain compatibility with changes in the CAD industry. |
Frontline PCB Solutions, DFM Tools:
Frontline Gensis 2000 is the CAM tool of choice used by ~80% of the PCB fabricators today.
As you can imagine when the fabricator finishes fine tuning your design with this CAM DFM tools your Gerbers may differ significantly from what was actually fabricated
Frontline Gensis 2000 is the CAM tool of choice used by ~80% of the PCB fabricators today.
As you can imagine when the fabricator finishes fine tuning your design with this CAM DFM tools your Gerbers may differ significantly from what was actually fabricated
Length Matching for High-Speed Differential Pairs
Tpd - One of my favorite topics.
http://pcdandf.com/cms/images/stories/mag/0502/0502strategies.pdf
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Tuesday, April 8, 2014
Friday, April 4, 2014
EEVblog #431 - PCB Wave Soldering - YouTube
This is old school wave soldering for ICs and surface mounted chip components.
This technique is rarely used today, re-flow ovens are preferred.
EEVblog #431 - PCB Wave Soldering - YouTube:
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This technique is rarely used today, re-flow ovens are preferred.
EEVblog #431 - PCB Wave Soldering - YouTube:
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Wednesday, April 2, 2014
Winonics | Printed Circuit Boards | Prototypes - Production - Quick Turn Arounds | Brea, CA
Winonics | Printed Circuit Boards | Prototypes - Production - Quick Turn Arounds | Brea, CA:
See Products and Services for DFM (Design for Manufacture) recommendations.
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See Products and Services for DFM (Design for Manufacture) recommendations.
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