Thursday, December 17, 2020

Mill-Max - SOLDER CUP CONNECTORS AND TERMINAL PINS

 


Wednesday, December 16, 2020

RF Design Reuse - Stackup Comments

For RF design reuse the 50 ohm trace width, distance to RF reference plane and PCB material need to be tightly constrained.

A well designed RF circuit can be moved to another PCB stackup provided the RF trace widths and dielectric thickness to the RF reference plane are nearly the same.  

RF matching work will be needed to optimize RF performance after changing stackups.

The Dielectric Constant (Dk or Er) is determined by the ratio of resin to glass.

The Dk of the material and distance to the reference plane determines the trace widths of the controlled impedances.

Dissipation Factor (Df or loss tangent). Low Df materials are preferred for RF performance.

Layer stackup considerations may include high-speed traces on outer layers which will require a thinner dielectric (~2.5mil) between L1 to L2.   A thicker dielectric (~3mil) can be used with a few impedance discontinuities and imperfections, i.e. trace width neck downs on the outer layers.

Vias in Pad Plated Over (VIPPO). RF designers appreciate VIPPO because it reduces the parasitics associated with vias and traces connected to RF components.

For fine pitch components in the design use thru-hole vias with a minimum size of 0.2mm / 0.45mm (drill / pads) or 8/18mil and very sparingly use 0.2mm / 0.4mm (8/16) where needed.

Use 10/22mil vias where possible.  Vias hole sizes should be 15mil or smaller to accommodate non-conductive fill and plated over vias ( VIPPO).

For high-speed designs consider using blind vias or back drilling a few thru-hole vias to reduce stub lengths. 

Blind vias may be less likely than thru-hole vias to experience via barrel fractures from repetitive thermal expansion in the Z axis,  Blind vias can also be useful where RF isolation is needed.

That it !

Thursday, December 3, 2020

LOCTITE STYCAST PC 40-UMF

Conformal coating is specifically formulated to rapidly gel and immobilize when exposed to UV light and then fully cure when exposed to atmospheric moisture, ensuring optimum performance even in shadowed areas. LOCTITE STYCAST PC 40-UMF conforms to IPC-CC-830 requirements.



Thursday, October 15, 2020

Thursday, October 8, 2020

Capacitors - Epoxy Mount only Automotive Grade

Something to be aware of when selecting capacitors ?

https://www.digikey.com/products/en?keywords=CGA2B3X7R1H104K050BB​​​​​​​

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MLCC Automotive grade CGA series - Sept 2020 Datasheet makes no mention of the Epoxy Mounting

MLCC Automotive grade CGA series - May 2019 Datasheet states . . . 

Conductive epoxy application CGA series, automotive grade of TDK's multilayer ceramic chip capacitor, is a product for conductive glue mounting, not for solder mounting. The risk of silver migration is reduced due to AgPdCu termination. The maximum operating temperature is 150°C and the capacitance range is up to 10µF.


That's It !


Saturday, July 11, 2020

Surviving the App Note Challenge - Design 007 (June 2020)

Design007 Magazine, June 2020

Hartley: I loved Lee Hill’s comment that he
made years ago. “When I’m doing a review of
a circuit with a problem, if I see more than one
ground, I know there’s money to be made.”

Gotta love that !



Monday, June 8, 2020

Stackup Request - Designer to Customer

We need to work with your preferred fabricator to create formal stackups.  

The overall board thickness, choice of materials (glass and resin) and the material Dk (dielectric constant) will determine precise trace widths and spaces for controlled impedance.

The ideal material for high-speed designs will have low a Df (dissipation factor) to minimize signal attenuation.  The length of the traces should be considered when selecting the materials.  If traces are short and wide then Df will not be a significant factor.  Low Df material is typically used on a high speed back planes and RF designs.  Note low Df materials are more expensive.

To maintain manufacturable trace widths as layer count increases where overall board thickness is ~80 mils or less the Dk needs to be lower than what is typically found on popular FR4 materials like 370HR.  FR408HR and GETEK are a popular choices for low Dk materials.

Fabricators prefer plated holes (vias) sized with 10:1 or less aspect ratio.  Where the aspect ratio is the overall board thickness divided by the drill hole size. 

Note drill/pad sizes 8/20mil (0.2/0.5mm) are needed to allow for routing diff pairs or two signal traces between the vias under 1mm pitch BGA and routing one trace between the vias 0.8mm pitch connectors.   

Please provide a email contact for your preferred fabricator.  We can work with your fabricator to design formal stackups and keep you in the loop (on the email threads).  

That's it !

Monday, May 11, 2020

Controlled Volume NPI - TTM

TTM is one of my favorite fabricators.  TTM has great customer service and excellent stackup designers.  Advanced and Engineering Capabilities.

So what is "Controlled Volume NPI" ?

This just a another buzzword for cutting edge (advanced) capabilities.

Example Controlled Volume NPI  Design Technology:

Drill / Pad = 8 / 16mil  (0.2 / 0.4mm) Thru-Hole Vias with VIPPO
Trace / Space = 3 / 3.25mil

As the title implies this is not high volume production. It is for low volume specialty designs which require special handling by a highly experienced fabricator with advanced capabilities.

And it's going to be a bit more expensive $$$

That's It !


Monday, May 4, 2020

10A 0402 Zero Ohm Resistor

For those times when you need a bigger zero ohm 0402 resistor :)

All zero ohm resistors are not equal and some maybe good fuses if your not careful.

KOA comes to the rescue. See KOA P/N TLRZ1ETTB

click on image to view.











That's it !

PCIE Express - AC Coupling Capacitors

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Source: https://community.nxp.com/thread/463277

Other Refs: 

xilinx - https://www.xilinx.com/support/answers/58921.html
Stack Exchange - Why Place Capacitors on PCIE Traces

That's it !