Xilinx Spartan-6 FPGA DDR3

• White Paper: Xilinx Spartan®-6 FPGA DDR3 Signal Integrity Analysis and PCB Layout Guidelines

DDR3 Design Requirements for KeyStone Devices

"This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) KeyStone series of DSP devices. The DDR3 interface supports 1600 MT/s and lower memory speeds in a variety of topologies (see the specific device Data Manual for supported speeds). This document assumes the user has a familiarization with DRAM implementation concepts and constraints."

Source: DDR3 Design Requirements for KeyStone Devices (Rev. B)

Definition of: MT/sec

MT/sec

(MegaTransfers per SECond) A measurement of bus and channel speed in millions of "effective" cycles per second. Also written as "MT/s," it is a rating of the actual, delivered speed rather than the frequency of the clock. For example, if timing is derived from both the rising and falling edges of the cycle rather than one complete cycle, a 400 MHz clock yields 800 MT/sec.

Source PC Mag: MT/sec Definition from PC Magazine Encyclopedia

DDR3 - Cycle Time

Clock Cycle time is the reciprocal of the base clock frequency.

DDR3-1066 = 266MHz base clock, or 3.75ns per cycle.
DDR3-1333 = 333MHz base clock, or 3.00ns per cycle.
DDR3-1600 = 400MHz base clock, or 2.50ns per cycle.
DDR3-2000 = 500MHz base clock, or 2.00ns per cycle

example: 1/266E10^6

equals 3.75nS

DDR3 Point-to-Point Design - Micron

TN-41-13: DDR3 Point-to-Point Design Support - Micron

DDR3 is an evolutionary transition from DDR2.


TN-52-02: LPDDR2/LPDDR3 Point-to-Point System - Micron

This technical note discusses guidelines to enhanced signal integrity (SI) and reduced noise for LPDDR2 and LPDDR3 devices in unterminated point-to-point and point-to-multipoint multilayer board designs.

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DDR3 Design Considerations for PCB Applications

Freescale AN111 - Jon Burnett

DDR3 Routing Guidelines

 click on image to view

Source:  http://www.slideshare.net/itzjishnu/ddr3 Jishnu Rajeev

Design Files for DDR3 240-pin Unbuffered DIMMs | JEDEC

Design Files for DDR3 240-pin Unbuffered DIMMs | JEDEC:

Registration is Free. Registered user can download DRR3 refernce designs.


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Length Matching for High-Speed Differential Pairs

Tpd - One of my favorite topics.

http://pcdandf.com/cms/images/stories/mag/0502/0502strategies.pdf


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Propagation Delay - Tpd

Lately I have been routing DDR3 designs and I'm keenly aware of Tpd. Why ?

Tpd = 1/(11.8/(SQRT(Keff)))*1000

Where Keff = the effective dielectric constant of the material surrounding the trace.

Let's say you have routed a portion of a DDR Data signal as a 50 Ohm 1 inch track on an outer layer, note Tpd ~ 139pSec per inch for a 50 Ohm microstrip.

And for the same net you have routed another 1 inch of track as 50 Ohm stripline on an inner layer, note Tpd = ~ 170pSec per inch for a 50 Ohm stripline.

Not counting for the Via length, the two inches of net routed as described above are 139pS + 170pS, which equals 309pSec.

As you can see if we are routing high speed signals with matched trace lengths then it matters what layer the traces are on.

Example:
2 inches of 50 Ohm microstrip = 2 x 139pS = 278pS
2 inches of 50 Ohm Stripline = 2 x 170pS = 340pS

That's big timing difference in terms of pSecs.  340pS - 278pS = 62pS

62pS would equal ~372mils of trace length.

Knowing Tpd and the length of your traces is critical for high speed designs.

Because signal velocity is FASTER FOR OUTER LAYER TRACES THAN FOR INNER LAYER TRACES, propagation delay is smaller for the outer layer.

There are fewer Tpd calculators available for differential pairs.  Differential pairs are slightly faster than single trace stripline conductors.  For a typical 100 Ohm differential pair Tpd ~ 155pSec per inch.

Clock skew needs to be considered in DDR3 length matching to the data lanes, therefore knowing the Tpd for the differential clock pairs is important.

Matched Timing:

To avoid timing mismatches designers often route data lanes on the same layers using equal trace lengths and geometry on each layer that the signals traverse.

Use the same number of vias in each signal routed. 

You may need to adjust the trace length for the differential pairs to match timing to the single-ended microstrip and stripline traces.

Tpd is propagation delay and V (velocity) is the reciprocal of Tpd. 

Example: if Tpd = 139pS/inch then V = 1/139 = 0.00719 inches per pSec.
Example: if Tpd = 170pS/inch then V = 1/170 = 0.00588 inches per pSec.

Rule of thumb: 
Typical FR4 material 6mils of trace is ~ 1 pSec.

That's it.

Analyzing DDR2/3/4 with Hyperlynx: - Mentor Graphics

On Demand Webinar

Analyzing DDR2/3/4 Memory Interfaces: Guarantee Your Margins Before You Build and Ship Boards - Mentor Graphics:

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DDRx Design Topologies

Source: TI App Note SPRAB11A

Typical DDR2 Balanced "T" Topology

Typical DDR3 Fly By Topology

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DDR2/3 Memory Made Easy - Ansoft Sims

Memory Made Easy DDR2/3 Analysis.pdf