DDR3 Design Requirements for KeyStone Devices

"This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) KeyStone series of DSP devices. The DDR3 interface supports 1600 MT/s and lower memory speeds in a variety of topologies (see the specific device Data Manual for supported speeds). This document assumes the user has a familiarization with DRAM implementation concepts and constraints."

Source: DDR3 Design Requirements for KeyStone Devices (Rev. B)