How to automate measurements with Python | EDN

How to automate measurements with Python | EDN:

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DDR4 SDRAM Memory Design Considerations

Memory Interfaces Design Hub - UltraScale DDR3/DDR4

UltraScale Architecture PCB Design DDR4 - UG583

Memory Interfaces - UltraScale DDR4/DDR3 Memory:

AN5097, Hardware and Layout Design ... - NXP

DDR4 Designing for Power and Performance - MemCon

DRAM Memory In High-Speed Digital Designs - Keysight

UltraScale Architecture PCB Design User Guide - xilinx

DRAM Memory In High-Speed Digital Designs - Micron

About split planes



Source: DRAM Memory In High-Speed Digital Designs - Micron


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Video Analysis of Solder Paste Release from Stencil Printing

Video Analysis of Solder Paste Release from Stencil Printing

"Solder paste release from the stencil is a critical factor in print quality, and ultimately, overall electronic product quality and reliability. To better understand release mechanics, an experiment was devised using a video microscope to capture the separation of the stencil from the PCB.

The experiment incorporates different aperture area ratios, solder pastes, stencil nanocoatings and underwipe solvents to visualize their effects on paste release. This study builds on previous research that developed the test setup and recording methods, and incorporates some modifications to the original experimental configuration to improve image quality.

The outputs of the experiments are videos that demonstrate the effects of solder paste formulation, solvent under wiping and nanocoating on paste release at different area ratios. The paper will discuss the observations from the videos, and the presentation will play the videos."

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DDR3 Design Requirements for KeyStone Devices

"This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) KeyStone series of DSP devices. The DDR3 interface supports 1600 MT/s and lower memory speeds in a variety of topologies (see the specific device Data Manual for supported speeds). This document assumes the user has a familiarization with DRAM implementation concepts and constraints."

Source: DDR3 Design Requirements for KeyStone Devices (Rev. B)

Definition of: MT/sec

MT/sec

(MegaTransfers per SECond) A measurement of bus and channel speed in millions of "effective" cycles per second. Also written as "MT/s," it is a rating of the actual, delivered speed rather than the frequency of the clock. For example, if timing is derived from both the rising and falling edges of the cycle rather than one complete cycle, a 400 MHz clock yields 800 MT/sec.

Source PC Mag: MT/sec Definition from PC Magazine Encyclopedia

DDR3 - Cycle Time

Clock Cycle time is the reciprocal of the base clock frequency.

DDR3-1066 = 266MHz base clock, or 3.75ns per cycle.
DDR3-1333 = 333MHz base clock, or 3.00ns per cycle.
DDR3-1600 = 400MHz base clock, or 2.50ns per cycle.
DDR3-2000 = 500MHz base clock, or 2.00ns per cycle

example: 1/266E10^6

equals 3.75nS

DDR3 Point-to-Point Design - Micron

TN-41-13: DDR3 Point-to-Point Design Support - Micron

DDR3 is an evolutionary transition from DDR2.


TN-52-02: LPDDR2/LPDDR3 Point-to-Point System - Micron

This technical note discusses guidelines to enhanced signal integrity (SI) and reduced noise for LPDDR2 and LPDDR3 devices in unterminated point-to-point and point-to-multipoint multilayer board designs.

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Giga Solution Tech > Wafer Test, Package Test, RF IC Test Service > Wafer Test

Giga Solution Tech > Wafer Test, Package Test, RF IC Test Service > Wafer Test:

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CheckSum - In-Circuit Test (ICT)

About CheckSum: 

"CheckSum In-Circuit Test (ICT) & On-Board Part Programming Systems CheckSum, LLC is a leading supplier of in circuit test and on-board gang programming systems and services to the worldwide electronics manufacturing industry."

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