PCB Designer: 2019

Saturday, November 23, 2019

PADS Designer - Unable to open iCDB connection. Solution #1 - YouTube

(10) PADS Designer - Unable to open iCDB connection. Solution #1 - YouTube

Solution 1

Solution 2

Select System Tools

Open Backup

Run Repair

Close and restart PADs

Thank you Pavel Serenok !

Saturday, May 11, 2019

Differential Pairs - Practical Design Constraints

High-speed

Differential Pair phase matching is length matching within the Differential Pair.

Practical High-speed Phase Matching is ~5% of the fastest transition time where the transition time is the rise or fall time, which ever edge is the fastest.

Below is a quote from PcbCart.

"Therefore, in the process of high-speed PCB design, relative delay of differential signal line in the routing regulation rules can be set to be 0.05 Tr (5% of fastest transition time) that is capable of meeting the requirement of signal integrity."

"The following three methods can be applied to obtain the value of Tr:

• Rise/fall time can be directly obtained from component manuals. However, in most situations, this parameter isn't provided.

• Value of Tr can be obtained from Ramp keywords from component IBIS (Input/Output Buffer Informational Specification) model. Rise/fall time parameters under Ramp keywords are generally measured at output port connected with a resistor of 50Ω, which are usually 20% to 80% of final voltage time. Since the parameters are obtained without considering the influence of package, it's strict for us to use rise/fall time as the value of Tr.

• The value of Tr can be estimated according to the minimum clock frequency or maximum clock frequency of output signals. Because distributive rise edge is approximately 10% of clock frequency in most high-speed digital systems, the value of Tr can be estimated with the minimum clock period Tclk provided based on formula: Tr = Tclk x 10%."

Source (link): PcbCart

Differential Isometric Processing and Simulation Verification of High-Speed Design

Here's some simple methods for calculating the 5% phase matching tolerance.

Using the Saturn PCB Toolkit

Select the Wavelength Calculator tab, select Period and input the transition time (Rise or Fall Time), slide the Wavelength Divider to 1/20 (note 1/20 = 5%).

click on image to view

If you can not find the transition time enter 1/10 of the clock period or enter the frequency multiplied by 10 and slide the Wavelength Divider to 1/20.

Note 1/20 = 5%.

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The frequency was multiplied by 10 because the transition time is approximately equal to 10% of the clock period and time is the reciprocal of frequency.

The period of 8000MHz is 1/8000Mhz = 125pSec

The period (reciprocal) of 800MHz is 1/800Mhz = 1.25nSec
The transition time (Rise or Fall time) is typically equal to the clock period divided by 10.

Low-speed

Next let's look at a Low Voltage Low Speed (32MHz) Differential Pair.

See Datasheet Page 6. AM26LV31E Low Voltage Differential Line Driver

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Note that the typical signal transition time (Tr) is 5nSec or 5000pSec.

5% of 5nSec = 0.25nSec = 250pSec

For typical FR4 with an Effective Er of 4 each pSec equals appropriately 6mils of trace.

Using this 5% of Tr thumb rule we have 250pSec * 6mils =1.5 inches for phase length matching the low-speed differential pairs.

click on image to view

Related Links:

See page 6 of this article by Lee Ritchey.

"LVDS is specified as working properly with length mismatches of 400 pSec. Converting this to a length results in a tolerance of approximately ±1200 mils or ±1.2 inches. Clearly, imposing a length matching requirement of ±10 mils is excessively tight."

Source: https://www.speedingedge.com/PDF-Files/DiffSigDesign.pdf

That's it !