NanoProof PCB Waterproof Treaments

NanoProof PCB Waterproof Treaments | No more Conformal Coatings! - Aculon:

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Rework Stencils, BGA Re-balling, Rework - X-Ray Inspection

Link: Rework Stencils, BGA Re-balling, Rework - X-Ray Inspection:

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Microstrip, Stripline, and CPW Design

This one of the bests RF transmission line articles you will find, it includes cover effects.

Microstrip, Stripline, and CPW Design

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Crosstalk - Guard Traces

"To be most effective, the guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor’s signal."

Source: Guard Traces White Paper -Issue 02 Lambert Simonvich

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Benefits of Coplanar Waveguide Over Ground

"Most RF designers use rules of thumb to space things appropriately. For instance, in microstrip design, many designers use a rule of thumb to keep topside copper away from their microstrip by four times the substrate layer thickness so as to not affect their microstrip impedance. With CPWG you don't have to worry about this since the topside ground is purposefully brought up next to the topside RF trace. But do you have to worry about that close board shield?"

Source: Article Benefits of Coplanar Waveguide Over Ground: Steve Hageman

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Benefits of Coplanar Waveguide Over Ground

Benefits of Coplanar Waveguide Over Ground: Steve Hageman

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Reduce Anti-Resonance in Decoupling Caps

The anti-resonance occurs at a frequency when one capacitor is still capacitive, while another has become inductive. 

Source: Take steps to reduce antiresonance in decoupling | EDN:

And 

Murata’s New ESR Capacitors Tackle Anti-Resonance

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PCB Design Perfection Starts in the CAD Library – Part 19 « Tom Hausherr's Blog

PCB Breakaway Panels

Mouse bites and V-Grove Scoring

Source:  PCB Design Perfection Starts in the CAD Library – Part 19 « Tom Hausherr's Blog:


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Via to Via Spacing

The Effect of Via Spacing on the Signal Integrity Performance of PCB with Slotted Ground

Via spacing on high-performance PCBs | EDN:


RELIABILITY TESTING FOR MICROVIAS IN PRINTED WIRE BOARDS


Proven microvia technology yields higher reliability because of the significantly lower area aspect ratio (1:1) due to its fabrication in one dielectric layer when compared to a larger drilled through-hole via having a much high aspect ratio (>10:1). 

Source: http://nepp.nasa.gov/docuploads/136AC3F6-8535-4E65-A0AD21B31AD56513/Microvia-2005E-Final-9-06.pdf


Costs

Click on Image to view

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Source: Design recommendations HDI – HDI Design Guide - Wurth


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