AMPSA - Home of RF Amplifier Design Excellence

Home of Amplifier Design Excellence:

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Qucs project: Quite Universal Circuit Simulator

Open Source Tool

Qucs project: Quite Universal Circuit Simulator:


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Field Solvers for Transmission Line Analysis: How Similar Are They?

Printed Circuit Design & Fab Online Magazine - Field Solvers for Transmission Line Analysis: How Similar Are They?:

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Microstrip Analysis/Synthesis Calculator - MIT

Microstrip Analysis/Synthesis Calculator:

A very good Online Java Calculator for Microstrip.

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An Overview of LPI Soldermask and the PCB Manufacturing Process

An Overview of LPI Soldermask and the PCB Manufacturing Process | Bay Area Circuits:














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Base Materials for High Speed and High Frequency Boards

Base Materials for High Speed, High Frequency PC Boards. 

By: Rick Hartley, March 2002, Published in PCB & A 

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Design Guidelines for Highspeed - Gbps Data Rates

Loss Tangent (Dissipation Factor) of PCB Materials

Source: Altera App Note 672

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See how easy it is to use the ODB++ viewer - Mentor Graphics

See how easy it is to use the ODB++ viewer to ensure your design intentions are correctly represented in your ODB++ manufacturing file in this demonstration video. - Mentor Graphics:

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RF Microwave Calculators

RF Calculators: Pasternack

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Microstrip - Solve for Wdth

EEE 244 -- What is a microstrip transmission line and how do you design one?

www.csus.edu/indiv/o/oldenburgj/eee244/chapter2/microstripdescompl.pdf

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Microstrip Analysis/Synthesis Calculator

Microstrip Analysis/Synthesis Calculator:

Online Java App

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AppCAD Version 4.0.0

AppCAD is one my personal favorites for RF calculations.

Link to AppCAd Home Page and Download: AppCAD:

click on image to view

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Velocity of Propagation | Wire & Cable VOP Effects

Aircraft Cable Velocity Factor | Velocity of Propagation | Wire & Cable VOP Effects: 

"Cable Velocity Factor Velocity Factor in Cables In theory, electrical signals move at the speed of light. Cables only slow them down. The ratio of actual speed to the speed of light is known as the velocity factor, or Velocity of Propagation (VOP), expressed as a percentage of the speed of light in free space."

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REFLOW SOLDERING - Better than Easy-Bake

click on image to view

Source: Reflow Soldering - Advanced Circuits

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3D CAD in the Cloud - Onshape

About Us | Onshape:

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Overlooking design-for-test can lead to costly PCB design rework | Embedded

Overlooking design-for-test can lead to costly PCB design rework | Embedded:

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Guidelines for SMT Assembly of 0201 DSN Package

Sources:

http://www.onsemi.com/pub_link/Collateral/AND9107-D.PDF

http://www.onsemi.com/pub_link/Collateral/AND8398-D.PDF


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Switching versus Linear Regulators

Excellent article for P/S design choices.

https://www.maximintegrated.com/en/app-notes/index.mvp/id/751

Power Distribution Network

The easy-to-use power distribution network (PDN) design tool is a graphical tool used with all Altera® FPGAs. 

Power Distribution Network:



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si-list Mailing List Archive

si-list Mailing List Archive: Signal Integrity

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How to measure propagation velocity

How to measure propagation velocity through a trace on a pcb? - Electrical Engineering Stack Exchange:

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Avoid PC-Layout "Gotchas" in ISM-RF Products - Tutorial - Maxim

Avoid PC-Layout "Gotchas" in ISM-RF Products - Tutorial - Maxim:

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Impedance Calculators - Mantaro Product Development Services

Impedance Calculators - Mantaro Product Development Services:

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High Speed Analog Design and Application Seminar

Section 1.  Understanding Voltage Feedback and Current Feedback Amplifiers
Section 2.  Useful Things to Know About Amplifiers
Section 3.  Useful Things to Know about A/D Converters
Section 4.  Selecting the right high-speed Amplifier
Section 5.  High-speed layout
Section 6.  Application design

Source: Texas Instruments

Via Calculations

Via Calculations

click on image to view

Source: 

High Speed Analog Design and Application Seminar
Section 5. - Texas Instruments


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Reference designator - Wikipedia, the free encyclopedia

Reference designator - Wikipedia, the free encyclopedia:


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Characterization of a Printed Circuit Board Via

"Design Guidelines

[1] Use the minimum size drill bit for creating the via cylinder. This has less to do with lowering the capacitance of the via and more to do with raising its inductance. Since a via looks like a region of low impedance compared to a traditional printed circuit board transmission line, raising the inductance will increase its characteristic impedance to better match the connecting lines. 

[2] Use the minimum size pad that the PCB manufacturer allows. The pad is the source of the most capacitance. The ideal case would be to connect the transmission lines directly to the via cylinder. 

[3] Do not use the minimum size ground clearance radius. This is counterintuitive since in most cases, smaller is better. By having a small portion of the connecting traces near the via NOT run over a ground plane, two regions of higher impedance immediately before and after the via are introduced. These regions of higher impedance will counter the lower impedance characteristic of the via and better match the line. This effect can also be accomplished by placing very small surface mount inductors in series with the via immediately before and after. 

[4] Use the thinnest printed circuit board possible. This will reduce the overall height of all vias on the board. Reducing the height of the via will decrease the length of the discontinuity that the signal has to pass through. 

[5] Place vias that connect the ground planes together near the signal vias that pass through multiple ground planes. This provides a low impedance path for the return current to flow when the signal changes layers. This will reduce the discontinuities caused by the via."

Source: www.coe.montana.edu/ee/lameres/vitae/publications/a_thesis/thesis_002_msee.pdf

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Microwaves101 | Keffective

Effective Er (Dk)

In all transmission lines, the propagation velocity is c/SQRT(Keff)

"K" refers to the effective dielectric constant, also called Epsilon_effective (Ee). 

Source: Microwaves101 | Keffective:


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Why Effective Er is not the same as Bulk Er - Polar Instruments

AP165 - Polar Instruments

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Learn how to design your own Arduino

Learn how to design your own Arduino:

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High Speed Board Layout Guidelines - Altera

click on image to see Altera App 224

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01005: Size Does Matter

Printed Circuit Design & Fab Online Magazine - 01005: Size Does Matter:

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Design Practices for Panelization and Depanelization

Printed Circuit Design & Fab Online Magazine - Design Practices for Panelization and Depanelization:

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Printed Circuit Design & Fab Online Magazine - How Hot Is My Via? (Cooler Than You Think!)

Printed Circuit Design & Fab Online Magazine - How Hot Is My Via? (Cooler Than You Think!):

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PDN Tool | Free Tool to Optimize Bypass Capacitors

PDN Tool | Free Tool to Optimize Bypass Capacitors:

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Problem with 'No Clean' Solder Flux Residue

Problem with 'No Clean' Solder Flux Residue:

Example:

“Just to be clear, no-clean does not mean that it does not have to be cleaned. It simply means that it leaves behind less residue than higher solids content fluxes. The residue is most likely lightly corrosive. The white residue is most likely unencapsulated metal salts. Conformal coating over the top of the residue is not recommend.

The potential for electro-migration is increased when flux (no-clean or otherwise) is allowed to stay on the assembly. It only takes three key ingredients to grow dendrites (metal crystals) on a board. These three ingredients are voltage, conductive / corrosive material (flux) and moisture (humidity). The flux residue forms a conductive path connecting an anode to a cathode. The results are either electrical leakage (a temporary problem) or dendrite growth (a permanent problem).”

Mike Konrad
Aqueous Technologies

Source: Experts opinions: http://www.circuitnet.com/experts/56589.html


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Cirris Systems - Flux Can Cause Opens or High Resistance

Cirris Systems - Flux Can Cause Opens or High Resistance:

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Understanding PCB Manufacturing: Hard Gold Plating

Understanding PCB Manufacturing: Hard Gold Plating: - Omni Circuits

Omni Circuits has an online Gold Calculator that can be used to estimate the amount of gold required to plate contacts.




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High Frequency VCO Design and Schematics

YO3DAC\Home Page

High Frequency VCO Designs

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DDR Memories Comparison and Overview|Freescale

DDR Memories Comparison and Overview|Freescale:

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Validation of DDR2/3 Designs

Validation of DDR2/3 Designs Agilent

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DDR Memory Layout Design: Rules, Factors, Considerations

Source: DDR Memory Layout Design: Rules, Factors, Considerations

Common length matching route groups are:

• Clock-to-Address/Command Group
• Clock-to-Strobes Group
• Strobe-to-Data Group

 Clock-to-Address/Command Group:

The purpose of the Clock-to-Address/Command Group (abbreviated CLK/ADDR/CMD) is to match the overall length of the CLK signal(s) to all ADDR and CMD signals specified. Depending on memory type, density, and bank structure, this group can get complicated, as there may be a complex signal topology scheme, which must be followed.

 Clock-to-Strobes Group (CLK/STB):

The requirement for the CLK/STB group is to match the overall total length of the CLK signal(s) to the Strobe and Data. This required group matching ties the CLK timing to the Data timing. The allowable matching tolerance is usually defined in the manufacturer’s data sheet.

 Strobe-to-Data Group (STB/Data):

The final group—STB/Data—should match the STB signal(s) to the individual Data bit signals. Since the number of signals that a Data group can contain may be large, the Data group is generally broken into “Data Byte Lanes.” Each lane contains eight Data bits, plus one Data mask, and one STB, and all signals in this group must be length matched to specification.

Layout Strategy:  (Suggested sequence of work)

Refer to applicable design guides for the memory controller.

Consider the IC package pin length data for accurate length matching.

Determine which pins can be swapped to simplify and optimize routing.

VREF trace width ~20mil.

Determine CK to DQSx skew and route path for Diff Pair DQSx.  

Because Differential Pairs i.e. DQSx, CLK and VREF tracks require wider paths, they should be routed first.  Keep in mind that all other signals in the data lanes or address /command bus will be matched length to the respective data strobe or clock.

Route data lanes, using only 2 vias per path and keep data lanes on same layer if possible. If it is not possible consider the flight time (Tpd) for each used layer and use the same number of vias in each path.  Data lanes are always point to point, unlike address / command lines data lanes are not branch or flyby routed.

For high-speed memory data lanes consider, Consider layer usage to minimize Via Stubs. Data rate is 2x faster than clock because data is latched on both rising and trailing clock edges.

Route address / command. Using only 2 vias per path and layers with similar flight times. If signals on the layers have significantly different flight times you should analyze or simulate the design.  Use appropriate branch, flyby or clam shell routing for address buses.

For flyby typologies and depending on the design tool used you may want to route each memory chip in sequence, i.e. finish routing the first chip and length matching the signals in the address / command bus before routing the next chip. This technique can be used with tools that report the total routed length along the path. Higher end tools include accurate pin to pin length data.

For a two chip DDR4 design use four inner layer signal layers alternating the layer usage across the two chips.

Place termination resistors ~1/2 inch or less beyond the last memory chip.  Distribute decoupling capacitors among the termination resistors, use one capacitor for every four resistors.

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DDR3 Design Considerations for PCB Applications

Freescale AN111 - Jon Burnett

TPS8267x 600-mA, High-Efficiency MicroSiP Step-Down Converter

The TPS8267x datasheet also has some good layout advice for uGBAs.

click on image to view

Source: http://www.ti.com/product/tps82671

DDR3 Routing Guidelines

 click on image to view

Source:  http://www.slideshare.net/itzjishnu/ddr3 Jishnu Rajeev

The Threat to Miniaturization of the Electronics Industry

Conductive Anodic Filament (CAF) - Park / Nelco 2004

This article is a bit dated, however it is still excellent reading for anyone who needs a refresher course for CAF.


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Digikey Part Finder – Speeds up building out BOMs | Reza's Rants

Digikey Part Finder – Speeds up building out BOMs | Reza's Rants:

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Filling mechanism in microvia metallization by copper electroplating

Filling mechanism in microvia metallization by copper electroplating:

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Design for Reliability: PCBs

Design for Reliability: DfR Solutions - Cheryl Tulkoff

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V-Scoring

Most modern CNC V-Scoring Machines are designed to hold at least +/-.002" on all dimensions (X, Y and Z).

V-Scoring FAQ's : AccuSystems

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V-scoring vs. Tab-Routing

V-scoring vs. Tab-Routing: "V-scoring vs. Tab-Routing"

1.6 to 2.0mm route is standard for routing.

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What’s The Difference: PCB Routing Then and Now | What’s The Difference Between… content from Electronic Design

What’s The Difference: PCB Routing Then and Now : Charles Pfeil

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PCB Router | Tab-Routed Boards | Fancort.com | Fancort®

PCB Router | Tab-Routed Boards | Fancort.com | Fancort®:

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PDF to Excel Converter – 100% Free

PDF to Excel Converter – 100% Free:

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Power Supply and Ground Design for a WiFi Transceiver - Tutorial - Maxim

Power Supply and Ground Design for a WiFi Transceiver - Tutorial - Maxim:

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Avoid PC-Layout "Gotchas" in ISM-RF Products - Tutorial - Maxim

Avoid PC-Layout "Gotchas" in ISM-RF Products - Tutorial - Maxim:

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High Performance Multilayer PCBs Design and Manufacturability

Transline Technology

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PCB Surface Finishes

PCB Surface Finishes – Implication on the SMT Process Yield.

Indium Corporation - Liyakathali.K

Excellent overview of surface finishes, includes Pros and Cons.

Design for Manufacturability (DFM) Tips

The suggestions in the link below are very conservative, not realistic for high density designs with fine pitch parts.  However good advice for simple low cost designs.

http://www.circuitservices.com/baretips.htm

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Conductive Fill or Non-Conductive Fill ?

“Which is the Best Choice for My Design?”

"90% or more products today specify non-conductive epoxy"

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How to Avoid Common Signal Integrity Issues in Your Designs

How to Avoid Common Signal Integrity Issues in Your Designs: - Barry Olney

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Fastpro - Metal Stamping

Etching, Laser cutting, Stampings, Sheet Metal, Machining and Welding

Lead time and costs are controlled because Faspro has photo etching, Laser cutting, heat treating, plating and forming in-house.

Faspro specializes in board shields, contacts, metal antennas and other thin gauge formed metal parts. 

Faspro checks for 100% shield coplanarity.

*Standard lead times are 5-12 business days but can be expedited in 2 days if needed.

*1 part to thousands of parts

*Only 3D models needed

*ITAR Registered

www.fasprotech.com

Voltera - Circuit Printer

Voltera - Circuit Printer:

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SMT Cable Clips | Harwin

Browse Products | Harwin:

click image to view

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EMI/RFI Shielding - Autosplice

EMI/RFI Shielding: Autosplice



Notes:

• Limited number of insertion cycles, clips will loose retention strength after the shields are pulled off and replaced.
• Pads and soldermask need to be tightly defined to accurately register the clips during reflow soldering. 
• Place covers on after testing and rework have been completed to minimize insertion cycles.

Fundamentals of PCB Design Abstract | TechOnline

Fundamentals of PCB Design Abstract | TechOnline:

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PCB and ESR subtleties in switching regulator and LDO designs | EDN

PCB and ESR subtleties in switching regulator and LDO designs | EDN: 

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Isola Group | I-Speed low-loss, high-speed material system.

Isola Group | I-Speed low-loss, high-speed material system.:

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IPC Document Revision Table

IPC Document Revision Table:

This where to go when you to determine if you have the latest revision of a IPC document.

Also see: IPC Standards SpecTree

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Gold Embrittlement in Lead-free Solder

http://www.smta.org/penang/presentations/s6_p3_chiu_alex.pdf


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How to Avoid Printed Circuit Board CAM Hold

How to Avoid Printed Circuit Board CAM Hold: Advanced Circuits

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Soldermask and QFPs

Here is an interesting statement about soldermask.

"By the way, don't assume that putting fingers of resist between pads on an otherwise bare board might help overcome bridging, because most bridging occurs between component leads above the board. You are just adding to the cost by using a more expensive process, and gaining little."

Source: PCB Solder Mask Design Basics - Standards, Materials and Processes:


Some points to consider:

Solder mask thickness is typically ~ 0.5mil thick.

Copper pads on outer layer are typically 1.4 to 2.0 mil thick. 

Solder paste thickness is typically ~ 5mil thick.

The copper pads are 3 to 4 times thicker (taller) than the soldermask.

The 5mil thick solder paste on top of copper pad is 10 times thicker (taller) than the soldermask.  

And the paste is sitting top of the copper pads.

click on image to view

Does soldermask between the pads really help prevent solder bridging ?

For fine pitch QFPs you may want to use ganged soldermask.

Something to think about.

Close up of solder paste on two adjacent pins.

That's It !

Screen and stencil printing

Screen and stencil printing:

The title says it ALL

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Evaluating DC-DC Converters

Evaluating DC-DC Converters and PDNwith the E5061B LF-RF Network Analyzer

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Thermal Management Solutions - Viasystems

Thermal Management Solutions - Viasystems: 

"DESIGN ADVANTAGES OF VIASYSTEMS PFC TECHNOLOGY"

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PCB Thermal Management - Stablcor

http://www.stablcor.com/data/STABLCOR_Presentation.pdf

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AN-2020 Thermal Design By Insight, Not Hindsight - TI

click on image to view

Source: www.ti.com/lit/an/snva419c/snva419c.pdf

Heat sinks - Micrel Application Hint 17

www.micrel.com/_PDF/App-Hints/ah-17.pdf

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Heatsink Mounting

http://www.pemnet.com/bulletins_A4/hscbdata_A4.pdf

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Heatsink USA

Heatsink USA:

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Soldermask thickness

Soldermask thickness:

Dated, but interesting dialog on SMT forum.

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Accredited Testing per ASTM, IPC, and MIL specs. | Trace Laboratories

Accredited Testing per ASTM, IPC, and MIL specs. | Trace Laboratories:

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Electrical Integrity: Signal and Power Integrity, Istvan Novak's home page

Electrical Integrity: Signal and Power Integrity, Istvan Novak's home page:

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Basic Principles of Signal Integrity - Altera White Paper

www.altera.com/literature/wp/wp_sgnlntgry.pdf

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Controlled Impedance Terminations

The DC termination has continuous current flow while the output is high.

click on image to view

The AC load termination has current flow during the edge transitions.

click on image to view

Related Link:
Transmission Line Terminations It’s The End That Counts! - Ultra CAD

Product Development Secrets from the Best Designers | Creation Technologies Blog

Product Development Secrets from the Best Designers | Creation Technologies Blog:

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INLYNK Software Inc. | Resource Management Solutions

INLYNK Software Inc. | Resource Management Solutions:

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Fabrication Services - San Diego, CA.

Fast5Protos
Hughes Circuits
Precision Circuits
U.S. Circuits