Autorouting Techniques.pdf (application/pdf Object)

Autorouting Techniques.pdf - Connect EDA

Vscore Central Pocket Guide to V-Scoring

The details are explained in at:
Vscore Central Pocket Guide to V-Scoring

Fab Houses - Capabilities

Alphabetical Order:



Optiprint

Transline Technolgy Incorporated

VIASYSTEMS

ZITROK - Metric Tolerances

DFT - Pogo Pins and Test Points Spacing

Spacing for Various Combinations of Pogo Pins placed adjacent to each other.


ECT

Distance from Component Edge to Center of Test Probe.
Probe Size              Distance in Inches
100mil Probe                  0.0430
75mil Probe                    0.0375
50mil Probe                    0.0350

RNS

Distance from Component Edge to Center of Test Probe.
100mil Probe                  0.0550


Standard Top Plate - For Components under .150".  

75mil Probe                    0.0450
50mil Probe                    0.0350
40mil Probe                    0.0350

Probe Size              Distance in Inches

click on image to view


Source RNS

Guide Lines:  Production Ready Programming

Listed below are some test-ability guide lines you should consider
during the PCB layout process:

1. When possible, all Bed-of-Nails ICT fixture probe locations using
designated test pads, thru-hole device pins, or unmasked vias,
should be provided on the secondary side (solder side) of the
PCB for all signal nets as well as all active unused device pins.

2. Top side probe locations should be kept to a minimum.

3. When possible, several power and ground probe locations should be
provided on the secondary side of the PCB for an even distribution
of the test system's power and ground probes.

4. ICT fixture probe locations should have a minimum pad size of
.025" diameter, and have an optimum center-to-center spacing of
.100". The minimum center-to-center spacing between ICT fixture
probe locations is .039". Standard center-to-center spacing between
ICT fixture probe types are: .100", .075", .050" and .039". However,
the .050" and .039" probe types should be avoided when possible.

5. ICT fixture probe locations should have an optimum distance of
.085" from any component body.

6. All selected vias used for ICT probe locations should be unmasked
and filled with solder. All other vias should also be filled or
covered with solder mask.

7. Both PCB components and ICT probe locations should not be placed
within .100" from the PCB edge.

8. Each PCB should have an optimum of two .125" non-plated tooling
holes in opposing corners.

Source of Guide Lines:


Production Ready Programming
Anaheim Ca. 92807-1816

4200 E. La Palma Ave.

Test Fixtures

Fixture Design Services:

ECT
RTI
RNS

Papers:
The Selection and Economics Of Wireless Test Fixtures - Teradyne Test 
Test Point Contact Reliability - ECT